Class information for: |
Basic class information |
| ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
|---|---|---|---|
| 29866 | 146 | 20.7 | 25% |
Classes in level above (level 2) |
| ID, lev. above |
Publications | Label for level above |
|---|---|---|
| 1040 | 9640 | JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//SINGLE EVENT UPSET SEU |
Terms with highest relevance score |
| Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|---|
| 1 | TRACE SIGNAL SELECTION | Author keyword | 6 | 80% | 3% | 4 |
| 2 | SILICON DEBUG | Author keyword | 5 | 40% | 7% | 10 |
| 3 | REAL TIME TRACE | Author keyword | 4 | 75% | 2% | 3 |
| 4 | TRACE BUFFER | Author keyword | 3 | 60% | 2% | 3 |
| 5 | POST SILICON VALIDATION | Author keyword | 2 | 23% | 6% | 9 |
| 6 | DESIGN FOR DEBUG DFD | Author keyword | 2 | 67% | 1% | 2 |
| 7 | ON CHIP DEBUGGER | Author keyword | 2 | 67% | 1% | 2 |
| 8 | PROCESSOR DEBUG | Author keyword | 2 | 67% | 1% | 2 |
| 9 | STATE RESTORATION | Author keyword | 2 | 67% | 1% | 2 |
| 10 | TRACE COMPRESSION | Author keyword | 2 | 36% | 3% | 4 |
Web of Science journal categories |
Author Key Words |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
|---|---|---|---|---|---|---|---|
| 1 | TRACE SIGNAL SELECTION | 6 | 80% | 3% | 4 | Search TRACE+SIGNAL+SELECTION | Search TRACE+SIGNAL+SELECTION |
| 2 | SILICON DEBUG | 5 | 40% | 7% | 10 | Search SILICON+DEBUG | Search SILICON+DEBUG |
| 3 | REAL TIME TRACE | 4 | 75% | 2% | 3 | Search REAL+TIME+TRACE | Search REAL+TIME+TRACE |
| 4 | TRACE BUFFER | 3 | 60% | 2% | 3 | Search TRACE+BUFFER | Search TRACE+BUFFER |
| 5 | POST SILICON VALIDATION | 2 | 23% | 6% | 9 | Search POST+SILICON+VALIDATION | Search POST+SILICON+VALIDATION |
| 6 | DESIGN FOR DEBUG DFD | 2 | 67% | 1% | 2 | Search DESIGN+FOR+DEBUG+DFD | Search DESIGN+FOR+DEBUG+DFD |
| 7 | ON CHIP DEBUGGER | 2 | 67% | 1% | 2 | Search ON+CHIP+DEBUGGER | Search ON+CHIP+DEBUGGER |
| 8 | PROCESSOR DEBUG | 2 | 67% | 1% | 2 | Search PROCESSOR+DEBUG | Search PROCESSOR+DEBUG |
| 9 | STATE RESTORATION | 2 | 67% | 1% | 2 | Search STATE+RESTORATION | Search STATE+RESTORATION |
| 10 | TRACE COMPRESSION | 2 | 36% | 3% | 4 | Search TRACE+COMPRESSION | Search TRACE+COMPRESSION |
Key Words Plus |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | DEBUG | 3 | 23% | 7% | 10 |
| 2 | VISIBILITY ENHANCEMENT | 2 | 67% | 1% | 2 |
| 3 | SILICON DEBUG | 1 | 33% | 2% | 3 |
| 4 | IC FAILURE ANALYSIS | 1 | 50% | 1% | 1 |
| 5 | SIGNAL SELECTION | 1 | 29% | 1% | 2 |
| 6 | TRACE SIGNAL SELECTION | 0 | 33% | 1% | 1 |
| 7 | FUNCTIONAL VALIDATION | 0 | 25% | 1% | 1 |
| 8 | PROGRAM EXECUTIONS | 0 | 20% | 1% | 1 |
| 9 | TOLERATING LATENCY | 0 | 20% | 1% | 1 |
| 10 | ASSERTION CHECKERS | 0 | 100% | 1% | 1 |
Journals |
Reviews |
| Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
|---|---|---|---|---|
| Debug support for complex systems on-chip: a review | 2006 | 40 | 4 | 50% |
| An infrastructure for debug using clusters of assertion-checkers | 2012 | 0 | 2 | 50% |
Address terms |
| Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | CHIP GENERATOR GRP | 1 | 50% | 0.7% | 1 |
| 2 | NETWORKING SYST | 1 | 50% | 0.7% | 1 |
| 3 | CUHK RELIABLE COMP | 0 | 33% | 0.7% | 1 |
| 4 | SYST INFRASTRUCT GRP | 0 | 33% | 0.7% | 1 |
| 5 | CORP IT | 0 | 17% | 0.7% | 1 |
| 6 | IC DESIGN DIGITAL DESIGN TEST | 0 | 14% | 0.7% | 1 |
| 7 | VEHICLE ELECT SYST | 0 | 14% | 0.7% | 1 |
| 8 | ADV COMP STUDY | 0 | 13% | 0.7% | 1 |
| 9 | AREA FIELDBUS CONTROL NETWORK DEV | 0 | 100% | 0.7% | 1 |
| 10 | CORE ARCHITECTURE GRP | 0 | 100% | 0.7% | 1 |
Related classes at same level (level 1) |
| Rank | Relatedness score | Related classes |
|---|---|---|
| 1 | 0.0000224251 | IBM SYST TECHNOL GRP//390//SERVER GRP |
| 2 | 0.0000199802 | DESIGN ERROR DIAGNOSIS//PASS FAIL INFORMATION//WITT POLYNOMIAL |
| 3 | 0.0000145952 | OPEN SOURCE OS//COMP ENGN COMP COMMUN//BOOTING TIME |
| 4 | 0.0000128626 | GRAY SHADES//COLUMN DRIVER//LCD DRIVER |
| 5 | 0.0000117292 | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION//IEEE MICRO//BRANCH PREDICTION |
| 6 | 0.0000104375 | TEXT COMPRESSION//ARITHMETIC CODING//HUFFMAN CODES |
| 7 | 0.0000091168 | TRANSITION FAULTS//FUNCTIONAL BROADSIDE TESTS//JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS |
| 8 | 0.0000077815 | REACHABILITY TESTING//RACE DETECTION//DATA RACE |
| 9 | 0.0000070627 | WORMHOLE ROUTING//NETWORK ON CHIP//NETWORK ON CHIP NOC |
| 10 | 0.0000068880 | INTELLECTUAL PROPERTY PROTECTION IPP//HARDWARE METERING//HARDWARE SECURITY |