Class information for: |
Basic class information |
| ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
|---|---|---|---|
| 9793 | 1055 | 15.8 | 36% |
Classes in level above (level 2) |
| ID, lev. above |
Publications | Label for level above |
|---|---|---|
| 1993 | 5054 | NANOELECT GIGASCALE SYST//ELECTROSTATIC DISCHARGE ESD//SILICON CONTROLLED RECTIFIER SCR |
Terms with highest relevance score |
| Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|---|
| 1 | NANOELECT GIGASCALE SYST | Address | 108 | 72% | 8% | 84 |
| 2 | ELECTROSTATIC DISCHARGE ESD | Author keyword | 106 | 43% | 18% | 191 |
| 3 | SILICON CONTROLLED RECTIFIER SCR | Author keyword | 77 | 72% | 6% | 61 |
| 4 | HOLDING VOLTAGE | Author keyword | 36 | 79% | 2% | 23 |
| 5 | ESD PROTECTION CIRCUIT | Author keyword | 35 | 89% | 2% | 16 |
| 6 | ESD PROTECTION | Author keyword | 25 | 45% | 4% | 41 |
| 7 | POWER RAIL ESD CLAMP CIRCUIT | Author keyword | 22 | 81% | 1% | 13 |
| 8 | SUBSTRATE TRIGGERED TECHNIQUE | Author keyword | 18 | 83% | 1% | 10 |
| 9 | LATCH UP | Author keyword | 16 | 30% | 4% | 44 |
| 10 | TRIGGER VOLTAGE | Author keyword | 15 | 67% | 1% | 14 |
Web of Science journal categories |
Author Key Words |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
|---|---|---|---|---|---|---|---|
| 1 | ELECTROSTATIC DISCHARGE ESD | 106 | 43% | 18% | 191 | Search ELECTROSTATIC+DISCHARGE+ESD | Search ELECTROSTATIC+DISCHARGE+ESD |
| 2 | SILICON CONTROLLED RECTIFIER SCR | 77 | 72% | 6% | 61 | Search SILICON+CONTROLLED+RECTIFIER+SCR | Search SILICON+CONTROLLED+RECTIFIER+SCR |
| 3 | HOLDING VOLTAGE | 36 | 79% | 2% | 23 | Search HOLDING+VOLTAGE | Search HOLDING+VOLTAGE |
| 4 | ESD PROTECTION CIRCUIT | 35 | 89% | 2% | 16 | Search ESD+PROTECTION+CIRCUIT | Search ESD+PROTECTION+CIRCUIT |
| 5 | ESD PROTECTION | 25 | 45% | 4% | 41 | Search ESD+PROTECTION | Search ESD+PROTECTION |
| 6 | POWER RAIL ESD CLAMP CIRCUIT | 22 | 81% | 1% | 13 | Search POWER+RAIL+ESD+CLAMP+CIRCUIT | Search POWER+RAIL+ESD+CLAMP+CIRCUIT |
| 7 | SUBSTRATE TRIGGERED TECHNIQUE | 18 | 83% | 1% | 10 | Search SUBSTRATE+TRIGGERED+TECHNIQUE | Search SUBSTRATE+TRIGGERED+TECHNIQUE |
| 8 | LATCH UP | 16 | 30% | 4% | 44 | Search LATCH+UP | Search LATCH+UP |
| 9 | TRIGGER VOLTAGE | 15 | 67% | 1% | 14 | Search TRIGGER+VOLTAGE | Search TRIGGER+VOLTAGE |
| 10 | ELECTROSTATIC DISCHARGE ESD PROTECTION | 13 | 62% | 1% | 13 | Search ELECTROSTATIC+DISCHARGE+ESD+PROTECTION | Search ELECTROSTATIC+DISCHARGE+ESD+PROTECTION |
Key Words Plus |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | ESD PROTECTION | 33 | 61% | 3% | 35 |
| 2 | PROTECTION DESIGN | 18 | 58% | 2% | 21 |
| 3 | FEEDBACK REGENERATIVE PROCESS | 17 | 100% | 1% | 8 |
| 4 | TRANSIENT POLE METHOD | 17 | 100% | 1% | 8 |
| 5 | LVTSCR | 15 | 82% | 1% | 9 |
| 6 | ESD PROTECTION DEVICES | 15 | 77% | 1% | 10 |
| 7 | HOLDING VOLTAGE | 15 | 77% | 1% | 10 |
| 8 | LATCH UP | 13 | 38% | 3% | 27 |
| 9 | CLAMP CIRCUITS | 9 | 67% | 1% | 8 |
| 10 | INPUT PADS | 8 | 70% | 1% | 7 |
Journals |
Reviews |
| Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
|---|---|---|---|---|
| A review on RF ESD protection design | 2005 | 57 | 8 | 63% |
| A review of electrostatic discharge (ESD) in advanced semiconductor technology | 2004 | 14 | 1 | 100% |
| Transient ionizing radiation effects in devices and circuits | 2003 | 25 | 42 | 43% |
| State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs | 1996 | 12 | 11 | 100% |
| ESD protection design for I/O libraries in advanced CMOS technologies | 2008 | 3 | 8 | 88% |
| Electrostatic discharge in semiconductor devices: Protection techniques | 2000 | 8 | 8 | 63% |
| ESD issues for advanced CMOS technologies | 1996 | 3 | 3 | 100% |
| Component level ESD testing | 1998 | 0 | 2 | 100% |
| Virtual optical experiments | 2005 | 0 | 55 | 20% |
Address terms |
| Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | NANOELECT GIGASCALE SYST | 108 | 72% | 8.0% | 84 |
| 2 | ESD | 13 | 41% | 2.3% | 24 |
| 3 | CORP ESD | 8 | 75% | 0.6% | 6 |
| 4 | ESD PROTECT TECHNOL | 6 | 100% | 0.4% | 4 |
| 5 | MIXED SIGNAL DEVICE TECHNOL | 4 | 75% | 0.3% | 3 |
| 6 | SOC TECHNOL | 4 | 29% | 1.1% | 12 |
| 7 | CORP PROC RELIABIL GRP | 3 | 100% | 0.3% | 3 |
| 8 | ESD ENGN | 3 | 100% | 0.3% | 3 |
| 9 | ESD PROD ENGN | 3 | 100% | 0.3% | 3 |
| 10 | DESIGN AUTOMAT TECHNOL | 3 | 60% | 0.3% | 3 |
Related classes at same level (level 1) |
| Rank | Relatedness score | Related classes |
|---|---|---|
| 1 | 0.0000085066 | AFDELING ESAT MICAS//ELECT ENGN MEASUREMENT SCI//INTENTIONAL ELECTROMAGNETIC INTERFERENCE IEMI |
| 2 | 0.0000071810 | ELECTROSTATIC DISCHARGE//ELECTROSTATICALLY INDUCED VOLTAGE//KKU SEAGATE COOPERAT |
| 3 | 0.0000069604 | SPECIFIC ON RESISTANCE//BREAKDOWN VOLTAGE BV//LDMOS |
| 4 | 0.0000065150 | COUPLED METHOD CM//MICROPARTICLE MANIPULATION//LEVELIZED |
| 5 | 0.0000062419 | CARL EMILY FUCHS MICROELECT//CEFIM//EUROPEAN QUAL |
| 6 | 0.0000053369 | SURGE PROTECTION DEVICE SPD//ELECTRIC SUBMERSIBLE PUMPS ESPS//PROTECTIVE DISTANCE |
| 7 | 0.0000053270 | HOT CARRIER//CHANNEL INITIATED SECONDARY ELECTRON CHISEL//HOT CARRIER DEGRADATION |
| 8 | 0.0000044739 | INSULATED GATE BIPOLAR TRANSISTOR IGBT//LATERAL INSULATED GATE BIPOLAR TRANSISTOR LIGBT//INSULATED GATE BIPOLAR TRANSISTORS IGBTS |
| 9 | 0.0000037825 | ELECTRON BEAM TESTING//SOREP//VOLTAGE CONTRAST |
| 10 | 0.0000037354 | RANGE PARAMETERS//SOFT ERROR MAPPING//HIGH ENERGY ION IMPLANTATION |