Receiving the good news from Luca Peretti back in 2022, I said to myself, “Yes! I finally joined a unique environment: the postdoctoral program focusing on total loss minimization. In the coming two years, I am going to dive into a new task at KTH Royal Institute of Technology.” I even said to myself that I am going to write a book by delicately presenting my experience from the rural mountains of Ethiopia all the way to China and then to Europe: Call it a personal biography if you may.
However, Youtube videos make it unbelievably terrible, and darkness shackles you to loneliness. Thus, I was in fear of the freezing weather. I asked everyone to gain knowledge about how to survive the winter. Yes, I received particularly useful comments on how to prepare for the winter. I also remember the Game of Thrones movie “Winter is Coming!” Man, this movie is a hell of a movie! It gave me a humble time during the Corona Outbreak. Once you start the game of the throne, there is no middle ground! Either you win or you lose. Anyhow, my appreciation goes to Matt, Yixuan, and Luca for giving me a remarkably useful suggestion. Therefore, I bought a winter jacket, shoes, etc. and prepared and geared up well.
My frustration with winter didn’t last long—I actually enjoyed my first snow and winter experience. It was truly fascinating! If there’s one thing I regret, it’s not trying ice skating. That would have been an unforgettable memory. My humble advice? Don’t trust those YouTube videos! They made it look terrifying, and I still hold a grudge against them for that.That said, be prepared for winter. Investing in the right clothing is essential to surviving and enjoying the season.
Having said a bit about my experience on the dark nights of Stockholm, let me take you to our project. First thing is first, I have been able to understand the concept of semiconductor loss and ways of improving semiconductor loss, either from a PWM perspective or a technological perspective. The semiconductor switching losses are directly proportional to the switching frequency of the inverter. Thus, having a reduced switching frequency is one of the approaches that could be adopted for motor drives. However, the noise and harmonic content of the motor current are vital to be considered. Therefore, a means of optimizing the switching frequency, loss, and current harmonic content is necessary. The introduction of selective harmonic elimination, the variable switching frequency approach, synchronous optimal PWM (SOPWM), and other approaches provide an alternative mechanism without changing the semiconductor technology. These approaches are somehow computationally intensive. Therefore, a less computationally intensive approach with good performance is vital. Proper modeling of the harmonic content of the motor current as well as the semiconductor losses of the inverter is equally vital.
The second approach involves utilizing wide-bandgap semiconductor devices, which are becoming essential in modern motor drives. Advanced semiconductor technologies like Silicon Carbide (SiC) and Gallium Nitride (GaN) enable operation at exceptionally high switching frequencies (in the MHz range). This results in reduced harmonics while simultaneously minimizing switching losses. Among these, GaN stands out for its superior performance. However, its blocking voltage capability limits its practical applications. For instance, commercially available GaN devices typically have a 650V blocking voltage, while companies like Infineon have developed GaN HEMTs with a blocking voltage range of 100V to 700V. The adoption of wide-bandgap technologies also facilitates the use of computationally efficient PWM techniques, such as Space Vector PWM (SVPWM) and carrier-based sinusoidal PWM. I had the privilege of working with Aurobay on leveraging GaN technology for loss minimization, which was an incredibly rewarding experience for me.
FPGA also provides a better digital control strategy. As such, I have been reading about how to implement the FPGA, which is fun to work on. Additional knowledge is accumulated along the way! My experience with FPGA programming has been quite surprising. While understanding the basics of FPGA programming wasn’t too difficult, working with the FMC112 ADC from ABACO turned out to be far more complex than expected. The manufacturer-provided code for the device is intricate, and I spent a significant amount of time trying to understand and debug it.
Despite my efforts, I kept encountering issues. Sometimes, I could receive the signal, but other times, it was completely absent. As a result, the AXI_STREAM_FIFO remained empty. Even when the signal was present, the data read from the FIFO was often zero, leaving me frustrated and confused—how was this even happening? After extensive debugging, I discovered that the problem originated in a specific section of the system, which I refer to as the “red box” in the data processing flow as shown in Fig. 1. If the system failed at this point, everything downstream would collapse. Further investigation suggested that the issue might be related to ADC triggering.
After struggling for a long time without a clear solution—despite reaching out to the manufacturer’s support—I decided to take a different approach. I bypassed the “red box” entirely and designed my own custom FIFO. My implementation takes the 16-bit signal from the FMC112, converts it to 64-bit, and incorporates a 64-depth FIFO memory, allowing for smoother data handling.
Fig. 1. A block representation of the ADC implementation
The newly designed FIFO successfully resolved my issue, allowing me to disable the “red box” from ABACO. What a relief after spending such a long- and frustrating-time debugging FPGA programming and deciphering the inner workings of the ABACO FMC112 model! Despite the challenges, this experience turned out to be incredibly valuable. It not only deepened my understanding of FPGA programming but also sharpened my problem-solving skills. Looking back, it was a tough but rewarding journey. The following figure shows the custom designed RTL.
Fig. 2. Designed 16to64 bit FIFO with a FIFO depth of 64
One important lesson I’ve learned is that failure is valuable. You can’t fail unless you take the initiative to start something. In this sense, my repeated struggles with implementing the ADC turned out to be an opportunity—it pushed me to dive deeper into FPGA programming and expand my understanding of this powerful technology. Had I succeeded immediately, I wouldn’t have explored FPGA programming in such depth. In retrospection, the challenges were not setbacks but a new path to greater knowledge and expertise.
In conclusion, this opportunity has truly opened new avenues for progress, from sensorless control of electrical machines to drivetrain loss modeling and the development of optimized drive systems. It has been a transformative experience, expanding my knowledge and skills in advanced motor drive technology.
Finally, you win the “Games of Throne”. It was a happy memory to take Feka with you, man.