Skip to content

Our Upcoming EuroSys 2019 Paper “Make the Most out of Last Level Cache in Intel Processors”

In our upcoming EuroSys 2019 paper, we exploit the characteristics of non-uniform cache architecture (NUCA) in recent Intel processors to introduce a new memory management scheme, i.e., slice-aware memory management. We believe that we are the first to: (i) take a step toward using the current hardware more efficiently in this manner, and (ii) advocate taking advantage of NUCA characteristics in LLC and allowing networking applications to benefit from it. In addition, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet’s header in the slice of the LLC that is closest to the relevant processing core. The results of our work showed that CacheDirector could reduce the tail latencies in latency-critical Network Function Virtualization (NFV) service chains by 21.5%. Furthermore, our work demonstrated that optimizing the computer systems and taking advantage of nanosecond improvements could have a higher impact on the performance of networking applications.​