Accelerating Computations with Field-Programmable Gate Arrays (FPGAs)

With the impending termination of Moore's law, researchers are actively searching for different forms of computing in order to continue providing faster and less power-hungry systems. Today, several such alternative architectures are emerging to fill the widening void arising from the end of Moore's law, including radical (and niche) systems such as quantum- and neuromorphic computers. However, out of the many proposed architectures, perhaps none is as salient an alternative as the Field-Programmable Gate Array (FPGA). FPGAs belong to the programmable logic device family of architectures, where they retain some of the reconfigurability that an Application-Specific Integrated Circuit (ASIC) system typically throws away. Facilitating such reconfigurability allows the silicon to be specialized for a particular application in order to (e.g.,) reduce data movement, improve performance, or improve energy efficiency.

In this docent lecture, I will present our efforts in creating custom FPGA-based accelerators to accelerate computational patterns found in scientific applications. I will start the lecture with an introduction and motivation to using FPGAs and position them against alternative Post-Moore technologies. I will then introduce how modern FPGAs are programmed using a methodology called High-Level Synthesis (HLS) and overview some use cases where we have applied HLS to accelerate key computations that yielded significant performance and/or power gains compared to existing state-of-the-art CPU and GPU solutions. I will end the lecture by discussing exciting future trends and emerging opportunities for reconfigurable computing in the decades to come.