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Silicon-Carbide-Based High-Voltage Submodules for HVDC Voltage-Source Converters

Time: Fri 2020-11-27 10.00

Location: Ångdomen, Kungl. Tekniska högskolans bibliotek, Osquars backe 31, Stockholm (English)

Subject area: Electrical Engineering

Doctoral student: Keijo Jacobs , Elkraftteknik, Power Electronics

Opponent: Prof. Dr.-Ing Marc Hiller, Karlsruher Institut für Technologie

Supervisor: Hans-Peter Nee, Elektrotekniska system, Elkraftteknik; Staffan Norrga, Elektrotekniska system, Elkraftteknik

Abstract

In order to transition to renewable energy sources and simultaneously meet the increasing demand for electrical energy, highly flexible and efficient grids are required. High-voltage direct-current (HVDC) transmission and grids are foreseen to be a vital part of the future electricity grid. Voltage source converters (VSCs), interfacing between HVDC and high-voltage alternating current (HVAC) technology, need to comply with grid code, and offer high reliability and cost efficiency. The state-of-the-art VSC topology is the modular multilevel converter (MMC), which offers tailored harmonic performance, modularity, fault handling, redundancy, and low losses.

This thesis investigates improvements for VSCs enabled by novel silicon carbide (SiC) power semiconductor devices. These devices feature lower losses, higher blocking voltage, and higher maximum operation temperature. However, a co-design of the different hardware levels (i.e., converter, submodule (SM), power device, and semiconductor) is required to unleash their full potential. The thesis features contributions on several of these hardware levels, aiming at improvements regarding defined technical requirements for VSCs.

It has been shown that, on converter level, future ultrahigh-voltage (UHV) SiC bipolar devices with blocking voltages of up to 50 kV have the potential for significant reduction of converter complexity, volume, and losses. The increased SM voltage is a challenge for internal fault handling, which can be met by a proposed novel SM feature, the discharge loop.

On SM level, additional improvements are enabled by synergies between power semiconductor device technology and SM topology. A comparative evaluation of a large variety of SM topologies in combination with different SiC power semiconductor device technologies identifies several promising design approaches for future SMs. An alternative to the state-of-the-art half-bridge and full-bridge SM is the semi-full-bridge, which is investigated intensively. It features lower switch count and lower losses compared to the full-bridge, while offering DC fault handling capability. Another topology, the double-connected double-zero SM, features additional conduction loss reduction in combination with SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), which is enabled by parallel current paths during certain switching states. A SM cluster enhancing this effect is proposed.

Finally, results on the optimization of SiC PiN diodes via different charge carrier lifetime tailoring methods are presented. The target application is a high-voltage high-frequency LCC converter. In the future, such diodes will also be required as anti-parallel diodes for novel UHV bipolar SiC devices, as bootstrap diodes in gate drivers, and as a part of snubber circuits.

urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284797