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Deep Neural Network Accelerator based on Networks-on-Chip

Time: Fri 2019-10-25 14.15

Location: Faculty Lounge, Kistagången 16, Kista

Participating: Masoumeh Ebrahimi, Department of Electronics and Embedded Systems (EES)

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Deep Neural networks (DNN) have shown significant improvements in many applications of artificial intelligence (AI) such as image classification and speech recognition. To support advanced DNN applications, networks must become larger and deeper, which demands a dramatic improvement in performance and power efficiency of computing platforms. The current general-purpose processors cannot process the large computations involved in DNNs with high performance. Thereby, the advancement of DNNs lies in the development of hardware platforms to execute them, which could enable the usage of AI applications to mobile and other edge devices. Currently, such services are provided through the cloud, running on CPUs or GPUs. However, cloud-based execution raises severe concerns about security, internet connectivity, and power consumption. In this docent presentation, conventional platforms and methodologies for DNN computing will be discussed. Then, a DNN accelerator design with a flexible interconnection network (i.e., Networks-on-Chip) will be explained. To achieve a better performance, different design parameters (e.g., topology, mapping algorithms, and routing algorithms) will be investigated on the introduced NoC-based DNN accelerator.