(50% PhD seminar) Hairpin Winding Designs to Minimize Interturn Voltage

Rising DC‑link voltages in electric vehicle powertrains increase the difficulty of achieving partial‑discharge‑free operation in inverter‑fed traction machines. Hairpin windings are especially affected, as simply increasing insulation thickness reduces slot fill factor and elevates copper losses. To avoid these drawbacks, redesigning the stator winding layout has emerged as a more effective strategy for limiting electrical stress.

A major driver of interturn voltage stress is the maximum sequence difference between series conductors placed in adjacent slot layers. By optimizing this sequence through modified connection schemes, interturn voltage stress can be substantially reduced. This work introduces and evaluates alternative hairpin winding architectures featuring two, three, and four parallel paths per phase, designed to maintain balanced electromagnetic performance while minimizing additional manufacturing effort.

In parallel, a coupled optimization of slot geometry, insulation thickness, and winding layout is performed to minimize copper losses while meeting torque and thermal limits at higher operating voltages. Parasitic capacitances are included to ensure that geometric changes do not counteract the intended electrical improvements.

The results show that optimized hairpin connection schemes offer a superior trade‑off between torque capability, copper losses, and insulation requirements, enabling more efficient high‑voltage electric machine designs.