Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
There is a video of this talk: www.youtube.com/watch?v=I3OEEBZ28aA
Speaker: Tage Mohammadat, KTH, Sweden
Title: Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.
Tage Mohammadat, is studying towards a doctorate degree in embedded computing system design and currently employed at the department of electronics, EECS/KTH. He obtained a master of science degree in system-on-chip design in 2016 from KTH Royal Institute of Technology. He hold a bachelor degree in electrical and electronic engineering from Universiti Teknologi Petronas, Perak, Malaysia in 2010.
He worked in various research and engineering projects within the context of electronic system design, e.g.: EU Horizon 2020 SAFEPOWER project (2.5 years), Artemis EMC2 (1.5 year), Resistive open fault testing in low power nanometric ICs (3 years), KTH student satellite project- SEUD experiment (1 year), Low-cost smart energy meter design (1 year). Currently partially with Vinnova NFFP7 Correct project and with CASTOR seed project on design space exploration.
His current research interests include: system-level architectural design of embedded computing systems, system-level design space exploration, low-power reliable electronics, safety-critical embedded systems.