Performance Techniques for Future High-Performance Computers
Speaker: Artur Podobas, RIKEN R-CCS (Processor Research Team)
Title: Performance Techniques for Future High-Performance Computers
In this talk, I will give an overview over the research I have been involved in during my past two years at Tokyo Institute of Technology. The primary focus of this talk will be various aspects of High-Performance Computing (HPC) including performance, benchmarking and compilers. From the performance part, I will talk about Field-Programmable Gate-Arrays (FPGAs) and their role in future HPC infrastructure, where we have shown that they can complement (and even compete with!) Graphic Processor Units (GPUs) and general-purpose processors (CPU). From the compiler part, I will present a transpiler that we built that allows to seamlessly enable OpenACC applications to leverage multiple discrete GPUs, including various optimization techniques. I will end by briefly describing our recent study where we question the need for the large amount of double-precision logic in modern processor architecture.
Artur Podobas defended his PhD thesis on on parallel prorgamming models and runtime systems in 2015 at the Royal Institute of Technology. His first postdoc position was at the Denmark Technical University (DTU Compute), working in the final year of the COPCAMS project. In 2016, he received the competitive Japan Society for the Promotion of Science (JSPS) postdoctoral scholarship, which he spent at professor Satoshi Matsuoka's laboratory at the Tokyo Institute of Technology. Current research interests include parallel programming models and runtime-systems, (reconfigurable-) architectures, and neuromorphic hardware.