IE1204 Digital Design 7.5 credits
Digital design
After completed course the student should be able to
-apply the basic teoretical knowledge for analysis and synthesis of combinatorial and sequential logic devices by
-chosing accurate practical problem solutions and simulation of designing digital devices
-describe digital components with hard desciption language (VHDL)
-explain the limitation of system performance designed in MOS-technoligy
Educational level
First cycleAcademic level (A-D)
ASubject area
Techonology
Grade scale
A, B, C, D, E, FX, F
Course offerings
Autumn 12 TIDAB TIEDB for programme students
Periods
Autumn 12 P2 (7.5 credits)
Application code
50793Start date
2012 week: 43End date
2013 week: 1Language of instruction
SwedishCampus
KTH KistaNumber of lectures
28 (preliminary)Number of exercises
16 (preliminary)Tutoring time
DaytimeForm of study
NormalNumber of places
No limitationSchedule
Schedule (new window)Course responsible
William Sandqvist <william@kth.se>
Teacher
Ingo Sander <ingo@kth.se>
Francesco Robino <frobino@kth.se>
Gunnar Johansson <gujo@kth.se>
Johnny Öberg <johnnyob@kth.se>
Fahimeh Jafari <fjafari@kth.se>
Seyed Hosein Attar Zadeh Niaki <shan2@kth.se>
Target group
Mandatory for TIDAB1 TIEDB1, but open for all programs
Part of programme
Autumn 13 TIDAB TIEDB for programme students
Periods
Autumn 13 P2 (7.5 credits)
Application code
50257Start date
2013 week: 45End date
2014 week: 3Language of instruction
SwedishCampus
KTH KistaNumber of lectures
28 (preliminary)Number of exercises
16 (preliminary)Tutoring time
DaytimeForm of study
NormalNumber of places *
Min. 25*) The Course date may be cancelled if number of admitted are less than minimum of places.
Schedule
Schedule (new window)Course responsible
William Sandqvist <william@kth.se>
Teacher
Gunnar Johansson <gujo@kth.se>
William Sandqvist <william@kth.se>
Ingo Sander <ingo@kth.se>
Johnny Öberg <johnnyob@kth.se>
Fahimeh Jafari <fjafari@kth.se>
Francesco Robino <frobino@kth.se>
Seyed Hosein Attar Zadeh Niaki <shan2@kth.se>
Target group
Mandatory for TIDAB1 TIEDB1, but open for all programs
Part of programme
Autumn 13 CINTE TKOMK for programme students
Periods
Autumn 13 P1 (7.5 credits)
Application code
50256Start date
2013 week: 36End date
2013 week: 44Language of instruction
SwedishCampus
KTH KistaNumber of lectures
28 (preliminary)Number of exercises
16 (preliminary)Tutoring time
DaytimeForm of study
NormalNumber of places *
Min. 25*) The Course date may be cancelled if number of admitted are less than minimum of places.
Schedule
Schedule (new window)Course responsible
William Sandqvist <william@kth.se>
Teacher
Francesco Robino <frobino@kth.se>
Ingo Sander <ingo@kth.se>
Fredrik L R Lundevall <flu@kth.se>
William Sandqvist <william@kth.se>
Fredrik Jonsson <fjon@kth.se>
Gunnar Johansson <gujo@kth.se>
Nan Li <nan3@kth.se>
Target group
Mandatory for CINTE1 and TKOMK1 but open for all programs
Part of programme
Learning outcomes
After completed course the student shall be able to
- use boolean algebra to describe and optimise logic functions
- draw and interpret schematics with symbols for logic gates and standard digital components
- analyse small combinational and sequential logic circuits and determine their functionality
- design small combinational and sequential logic circuits which implement a given function
- implement small combinational and sequential logic circuits with standard components and be able to find wrong connections
- use tools for simulation of combinational and sequential digital circuits
- determine the functionality of small digital circuits that are described using a hardware description language
- give the functionality of simple CMOS-schematics by a boolean equation
- understand how the physical properties affect the timing characteristics of digital circuits
Course main content
Number System and Codes. Binary Arithmetic. Booolean algebra and Booolean functions. Logic operations. Logic gates. Optimisation methods. Combinational function blocks. Digital arithmetic. Design of combinational circuits. Latches and Flips-Flops. Counters. Sequential circuits. Finite state diagrams. Finite state machine of Mealy and Moore type. Asynchronous sequential circuits. Design of synchronous and asynchronous sequential circuits. Programmable logic. Introduction to VHDL. Memory. Fundamental MOS-technology.
Eligibility
Completed upper secondary education including documented proficiency in Swedish corresponding to Swedish B and English corresponding to English A. For students who received/will receive their final school grades after 31 December 2009, there is an additional entry requirement for mathematics as follows: documented proficiency in mathematics corresponding to Mathematics A. And the specific requirements of mathematics, physics and chemistry corresponding to Mathematics D, Physics B and Chemistry A.
Literature
Stephen Brown och Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 2009.
Examination
- LABA - Laboratory Work, 3.5 credits, grade scale: P, F
- TENA - Examination, 4.0 credits, grade scale: A, B, C, D, E, FX, F
Requirements for final grade
For the final grade all examination parts (exam and laboratory course) have to be passed.
Offered by
ICT/Electronic Systems
Examiner
Ingo Sander <ingo@kth.se>
Supplementary information
The course is given several times during a study year.
Version
Course plan valid from:
Autumn 11.
Examination information valid from:
Autumn 10.
