This course has been discontinued.
Last planned examination: Spring 2000
Decision to discontinue this course: No information inserted

Course offering missing
Course offering missing for current semester as well as for previous and coming semestersContent and learning outcomes
Course contents
- ASIC design flow
- ASIC technologies
- Classification and specification constraints for logic synthesis
- Static timing analysis
- State machine synthesis
- Test and verification
- Low power design and logic synthesis
- Design for testability
- Technology mapping
- Physical design issues
Intended learning outcomes
After the course the student shall be able to
- describe the different phases of the design flow for digital ASICs
- explain how non-functional design constraints affect the design process
- categorize different types of ASICs and explain their technology
- explain how hardware description language patterns are realized in hardware
- introduce extra hardware in order to improve the testability of a design
- name and explain techniques for the test and verification of a design
- control the design process by assigning constraints and properties in order to yield an efficient implementation of a design
- write a design specification using a hardware description languages in such a way that it can be efficiently implemented in an ASIC
- apply techniques to analyze the timing of the final implementation
Course Disposition
No information inserted
Literature and preparations
Specific prerequisites
IL2217 or similar.
Recommended prerequisites
No information inserted
Equipment
No information inserted
Literature
The course book is announced on the course web page one month before course start.
Examination and completion
If the course is discontinued, students may request to be examined during the following two academic years.
Grading scale
A, B, C, D, E, FX, F
Examination
- LAB1 - Laboratory Course, 3,0 hp, betygsskala: P, F
- TEN1 - Examination, 4,5 hp, betygsskala: A, B, C, D, E, FX, F
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
Grading scale: A/B/C/D/E/Fx/F
Other requirements for final grade
Written exam, 4.5 hp (TEN1: Grade A-F)
Laboratory course, 3.0 hp (LAB1: Grade P, F)
The grade of the written exam (TEN1) is also the final grade of the course.
The lab course must be completed during the study year. If the course is not completed during the study year old laboratories are not counted anymore.
Opportunity to complete the requirements via supplementary examination
No information inserted
Opportunity to raise an approved grade via renewed examination
No information inserted
Examiner
Ethical approach
- All members of a group are responsible for the group's work.
- In any assessment, every student shall honestly disclose any help received and sources used.
- In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.
Further information
Course web
Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.
Course web IL2200Offered by
Main field of study
Electrical Engineering
Education cycle
Second cycle
Add-on studies
No information inserted
Contact
Ahmed Hemani
Supplementary information
ASIC = Application Specific Integrated Circuit
FPGA = Field Programmable Gate Array
VHDL = VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit