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IE1205 Digital Design 6.0 credits

After completed course the student should be able to 
-apply the basic teoretical knowledge for analysis and synthesis of combinatorial and sequential logic devices by
-chosing accurate practical problem solutions and simulation of designing digital devices
-explain the limitation of system performance designed in MOS-technoligy

Choose semester and course offering

Choose semester and course offering to see current information and more about the course, such as course syllabus, study period, and application information.


For course offering

Autumn 2024 CELTE programme students

Application code


Headings with content from the Course syllabus IE1205 (Spring 2019–) are denoted with an asterisk ( )

Content and learning outcomes

Course contents

Number System and Codes. Binary Arithmetic. Booolean algebra and Booolean functions. Logic operations. Logic gates. Optimisation methods. Combinational function blocks. Digital arithmetic. Design of combinational circuits. Latches and Flips-Flops. Counters. Sequential circuits. Finite state diagrams. Finite state machine of Mealy and Moore type. Asynchronous sequential circuits. Design of synchronous and asynchronous sequential circuits. Programmable logic. Introduction to VHDL. Memory. Fundamental MOS-technology.

Intended learning outcomes

After completed course the student shall be able to

- use boolean algebra to describe and optimise logic functions

- draw and interpret schematics with symbols for logic gates and standard digital components

- analyse small combinational and sequential logic circuits and determine their functionality

- design small combinational and sequential logic circuits which implement a given function

- use tools for simulation of combinational and sequential digital circuits

- determine the functionality of small digital circuits that are described using a hardware description language

- give the functionality of simple CMOS-schematics by a boolean equation

- understand how the physical properties affect the timing characteristics of digital circuits

Literature and preparations

Specific prerequisites

No information inserted

Recommended prerequisites

No information inserted


No information inserted


Digital Design and Computer Architecture, 2nd edition, David Money Harris and Sarah L. Harris, Morgan Kaufmann 2013, ISBN 978-0-12-394424-5


Digital Design and Computer Architecture, Arm Edition, David Money Harris and Sarah L. Harris, Morgan Kaufmann 2015, ISBN 978-0-12-800056-4

Examination and completion

If the course is discontinued, students may request to be examined during the following two academic years.

Grading scale

A, B, C, D, E, FX, F


  • LAB1 - Laboratory Work, 2.0 credits, grading scale: P, F
  • TEN1 - Examination, 4.0 credits, grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Other requirements for final grade

For the final grade all examination parts (TEN1 and LAB1) have to be passed.

Opportunity to complete the requirements via supplementary examination

No information inserted

Opportunity to raise an approved grade via renewed examination

No information inserted


Ethical approach

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Further information

Course room in Canvas

Registered students find further information about the implementation of the course in the course room in Canvas. A link to the course room can be found under the tab Studies in the Personal menu at the start of the course.

Offered by

Main field of study


Education cycle

First cycle

Add-on studies

No information inserted

Supplementary information

In this course, the EECS code of honor applies, see: