Decision to discontinue this course:
No information inserted
Course offerings are missing for current or upcoming semesters.
Please note: all information from the Course syllabus is available on this page in an accessible format.
Course syllabus IL2204 (Autumn 2008–)Introduction to analog and digital filters. Applied signal processing.
Design methods for data intensive applications, for instance, within Digital Signal Processing and Telecommunication: Allocation, Scheduling, Binding, Pipelining, Retiming, Bit-serial Design.
Implementation methods for digital filter functions (FIR, IIR, FFT). FPGA-synthesis of filter functions. The DSP processor. DSP-cores as part of an embedded system. A/D and D/A-conversion.
After finished course the student should be able to
1) use Control and Data Flow Graphs (CDFGs) to model and implement known digital signal processing functions (FIR/IIR/FFT) on FPGAs.
2) make calculations on the effects/limitations that the selection of datatype/resolution has on the implementations of known DSP-functions.
3) understand and utilize the addressing of memories to the DSP-functions for the optimization of them.
4) optimize the implementation wrt area/delay/latency/power consumption.
5) build prototypes of DSP-cores on FPGAs.
Lecture notes (pdf/ppt-format).
3 Laboration instructions (published on the course web page).
Additional material not contained in the course book.
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
If the course is discontinued, students may request to be examined during the following two academic years.
Grading scale: A/B/C/D/E/Fx/F
One written exam (TEN1 3hp),
passed laboration course (LAB1 4.5hp) with 2 obligatory laborations (FIR-filter and FFT).
The laborations are driven in project form. The students are supposed to work independently on their own in groups of maximum two students, without any help from the lab assistants. The lab assistants are available for tool support only, and for checking finished lab projects.
For each lab, a short laboration report (~2-3 pages) documenting all results obtained should be submitted to the assistants before the assistants will come and check the simulations and the working FPGA prototype.
The course is examined continously. Each passed laboration also has the function of a minor examination which gives bonus points for the written exam. The number of points depends on the quality of the solution. Note! Laboration points are a speed bonus to the exam. To get the points, the labs have to be completed and approved by an assistant before the first examination occasion. The laborations may contribute with the following points to the exam: Laboration 1 - FIR-filter 2pLaboration 2 - FFT-processor 2p Optional extra lab for fast students (mandatory to get grade A) Laboration 3 - Bit-serial design 1p A student is guaranteed to pass the exam if the student has at least 15 points of maximum 30 (50% correct). A student that has passed all laborations before the first exam has automatically 4 points (5 points with the Bit-serial lab) on the exam and hence needs only to get eleven (ten with the bit-serial lab) points on the exam to achieve the grade E.
