Last planned examination: Spring 2020
Decision to discontinue this course:
No information inserted
System-on-chip architectures
- System-on-chip design flow
- System-on-chip platforms
- On-chip buses: cache coherence, bus protocols, arbitration techniques
- Network-on-chip: topology, routing, flow control, quality of service, router architecture, network interface
After finishing the course the student shall be able to
- explain the importance of an efficient system-on-chip communication infrastructure
- explain how design platforms can be used for an efficient design process
- categorize properties of different bus architectures
- compare bus-based and network-on-chip based architectures and point out strength and weaknesses
- motivate how topology, routing mechanisms and flow control influence the performance of a network-on-chip
- describe the design process for complex systems-on-chip
The course requires good knowledge of
- the design of embedded computer systems corresponding to IL2206 Embedded Systems.
- the design process of digital hardware corresponding to IL2217 Digital Design with HDL
Principles and Practices of Interconnection Networks, William James Dally and Brian Towles
Upplaga: Förlag: Morgan Kaufmann År: 2004
ISBN: 0-12-200751-4
If the course is discontinued, students may request to be examined during the following two academic years.
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
Written exam (TEN1: Grade A-F)
Laboratory course (LAB1: Grade P, F)
The grade of the written exam (TEN1) is also the final grade of the course.
The lab course must be completed during the study year. If the course is not completed during the study year old laboratories are not counted anymore.
