Publications by Gunnar Malm

Refereegranskade

Artiklar

[1]

C. C. M. Capriata and B. G. Malm, "Grain structure influence on synchronized two-dimensional spin-Hall nano-oscillators," AIP Advances, vol. 13, no. 5, 2023.

[2]

C. C. M. Capriata et al., "Impact of Random Grain Structure on Spin-Hall Nano-Oscillator Modal Stability," IEEE Electron Device Letters, vol. 43, no. 2, pp. 312-315, 2022.

[3]

D. Ramos Santesmases et al., "1/f Noise and Dark Current Correlation in Midwave InAs/GaSb Type-II Superlattice IR Detectors," Physica Status Solidi (a) applications and materials science, vol. 218, no. 3, pp. 2000557, 2021.

[4]

A. J. Eklund et al., "Impact of intragrain spin wave reflections on nanocontact spin torque oscillators," Physical Review B, vol. 103, no. 21, 2021.

[5]

S. Hou et al., "A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C," IEEE Journal of the Electron Devices Society, vol. 8, no. 1, pp. 116-121, 2020.

[6]

M. W. Hussain et al., "A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications," IEEE Journal of the Electron Devices Society, vol. 7, no. 1, pp. 191-195, 2019.

[7]

M. W. Hussain et al., "An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)," IEEE Transactions on Electron Devices, vol. 66, no. 8, pp. 3694-3694, 2019.

[8]

M. Ekström, B. G. Malm and C.-M. Zetterling, "High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators," IEEE Electron Device Letters, vol. 40, no. 5, pp. 670-673, 2019.

[9]

M. Shakir et al., "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications," Electronics, vol. 8, no. 5, 2019.

[10]

M. Shakir et al., "A 600 degrees C TTL-Based 11-Stage Ring Oscillator in Bipolar Silicon Carbide Technology," IEEE Electron Device Letters, vol. 39, no. 10, pp. 1540-1543, 2018.

[11]

A. Abedin et al., "Germanium on Insulator Fabrication for Monolithic 3-D Integration," IEEE Journal of the Electron Devices Society, vol. 6, no. 1, pp. 588-593, 2018.

[12]

C.-M. Zetterling et al., "Bipolar integrated circuits in SiC for extreme environment operation," Semiconductor Science and Technology, vol. 32, no. 3, 2017.

[13]

S. A. H. Banuazizi et al., "Order of magnitude improvement of nano-contact spin torque nano-oscillator performance," Nanoscale, vol. 9, no. 5, pp. 1896-1900, 2017.

[14]

A. D. Smith et al., "Wafer-Scale Statistical Analysis of Graphene FETs-Part I : Wafer-Scale Fabrication and Yield Analysis," IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3919-3926, 2017.

[15]

A. D. Smith et al., "Wafer-Scale Statistical Analysis of Graphene Field-Effect Transistors-Part II : Analysis of Device Properties," IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3927-3933, 2017.

[16]

R. Hedayati et al., "A 500 degrees C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology," IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3445-3450, 2016.

[17]

T. Chen et al., "Spin-Torque and Spin-Hall Nano-Oscillators," Proceedings of the IEEE, vol. 104, no. 10, pp. 1919-1945, 2016.

[18]

T. Chen et al., "Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I : Analytical Model of the MTJ STO," IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 1037-1044, 2015.

[19]

T. Chen et al., "Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II : Verilog-A Model Implementation," IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 1045-1051, 2015.

[20]

S. Bonetti et al., "Direct observation and imaging of a spin-wave soliton with p−like symmetry," Nature Communications, vol. 6, 2015.

[21]

L. Lanni et al., "ECL-based SiC logic circuits for extreme temperatures," Materials Science Forum, vol. 821-823, pp. 910-913, 2015.

[22]

M. Östling and B. G. Malm, "Editorial Selected papers from the 15th Ultimate Integration on Silicon (ULIS) conference," Solid-State Electronics, vol. 108, pp. 1-1, 2015.

[23]

L. Lanni et al., "Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs," IEEE Electron Device Letters, vol. 36, no. 1, pp. 11-13, 2015.

[24]

T. Chen et al., "Integration of GMR-based spin torque oscillators and CMOS circuitry," Solid-State Electronics, vol. 111, pp. 91-99, 2015.

[25]

M. Olyaei et al., "Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs," IEEE Electron Device Letters, vol. 36, no. 12, pp. 1355-1358, 2015.

[26]

R. Hedayati et al., "A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology," IEEE Electron Device Letters, vol. 35, no. 7, pp. 693-695, 2014.

[27]

A. Eklund et al., "Dependence of the colored frequency noise in spin torque oscillators on current and magnetic field," Applied Physics Letters, vol. 104, no. 9, pp. 092405, 2014.

[28]

S. S. Suvanam et al., "Effects of 3-MeV Protons on 4H-SiC Bipolar Devices and Integrated OR-NOR Gates," IEEE Transactions on Nuclear Science, vol. 61, no. 4, pp. 1772-1776, 2014.

[29]

L. Lanni et al., "Lateral p-n-p Transistors and Complementary SiC Bipolar Technology," IEEE Electron Device Letters, vol. 35, no. 4, pp. 428-430, 2014.

[30]

L. Lanni et al., "SiC Etching and Sacrificial Oxidation Effects on the Performance of 4H-SiC BJTs," Materials Science Forum, vol. 778-780, pp. 1005-1008, 2014.

[31]

L. Lanni et al., "500 degrees C Bipolar Integrated OR/NOR Gate in 4H-SiC," IEEE Electron Device Letters, vol. 34, no. 9, pp. 1091-1093, 2013.

[32]

L. Lanni et al., "A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits," Journal of Microelectronics and Electronic Packaging, vol. 10, no. 4, pp. 155-162, 2013.

[33]

L. Lanni et al., "High-temperature characterization of 4H-SiC darlington transistors for low voltage applications," Materials Science Forum, vol. 740-742, pp. 966-969, 2013.

[34]

S. Redjai Sani et al., "Mutually synchronized bottom-up multi-nanocontact spin-torque oscillators," Nature Communications, vol. 4, pp. 2731, 2013.

[35]

K. -. Persson, B. G. Malm and L. -. Wernersson, "Surface and core contribution to 1/f-noise in InAs nanowire metal-oxide-semiconductor field-effect transistors," Applied Physics Letters, vol. 103, no. 3, pp. 033508, 2013.

[36]

A. C. Fischer et al., "3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching," Advanced Functional Materials, vol. 22, no. 19, pp. 4004-4008, 2012.

[37]

M. M. Naiini et al., "ALD high-k layer grating couplers for single and double slot on-chip SOI photonics," Solid-State Electronics, vol. 74, pp. 58-63, 2012.

[38]

L. Lanni et al., "Bipolar integrated OR-NOR gate in 4H-SiC," Materials Science Forum, vol. 717-720, pp. 1257-1260, 2012.

[39]

L. Lanni et al., "Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC," IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 1076-1083, 2012.

[40]

C.-M. Zetterling et al., "Future high temperature applications for SiC integrated circuits," Physica Status Solidi. C, Current topics in solid state physics, vol. 9, no. 7, pp. 1647-1650, 2012.

[41]

B. Buono et al., "Investigation of Current Gain Degradation in 4H-SiC Power BJTs," Materials Science Forum, vol. 717-720, pp. 1131-1134, 2012.

[42]

M. Olyaei et al., "Low-Frequency Noise in High-k LaLuO₃/TiN MOSFETs," Solid-State Electronics, vol. 78, no. SI, pp. 51-55, 2012.

[43]

K. B. Gylfason et al., "Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching," Journal of Vacuum Science & Technology B, vol. 30, no. 6, pp. 06FF05, 2012.

[44]

B. Buono et al., "Current Gain Degradation in 4H-SiC Power BJTs," Materials Science Forum, vol. 679-680, pp. 702-705, 2011.

[45]

M. Östling, G. Malm and H. H. Radamson, "Foreword," Solid-State Electronics, vol. 60, no. 1, 2011.

[46]

L. Donetti et al., "Hole effective mass in silicon inversion layers with different substrate orientations and channel directions," Journal of Applied Physics, vol. 110, no. 6, pp. 063711, 2011.

[47]

L. Lanni et al., "Measurements and simulations of lateral PNP transistors in a SiC NPN BJT technology for high temperature integrated circuits," Materials Science Forum, vol. 679-680, pp. 758-761, 2011.

[48]

B. Buono et al., "Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs," IEEE Transactions on Electron Devices, vol. 58, no. 7, pp. 2081-2087, 2011.

[49]

B. Buono et al., "Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs," IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2664-2670, 2010.

[50]

B. Buono et al., "Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs," IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 704-711, 2010.

[51]

S. Persson et al., "Strained-Silicon Heterojunction Bipolar Transistor," IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1243-1252, 2010.

[52]

B. Buono et al., "Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs," Materials Science Forum, vol. 645-648, pp. 1061-1064, 2010.

[53]

R. Ghandi et al., "High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension," IEEE Electron Device Letters, vol. 30, no. 11, pp. 1170-1172, 2009.

[54]

F. Driussi et al., "On the electron mobility enhancement in biaxially strained Si MOSFETs," Solid-State Electronics, vol. 52, no. 4, pp. 498-505, 2008.

[55]

Z. Zhang et al., "SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation," IEEE Electron Device Letters, vol. 29, no. 1, pp. 125-127, 2008.

[56]

A. Berrier et al., "Carrier transport through a dry-etched InP-based two-dimensional photonic crystal," Journal of Applied Physics, vol. 101, no. 12, pp. 123101-1-123101-6, 2007.

[57]

M. von Haartman et al., "Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs," Solid-State Electronics, vol. 51, no. 5, pp. 771-777, 2007.

[58]

J. Hållstedt et al., "A robust spacer gate process for deca-nanometer high-frequency MOSFETs," Microelectronic Engineering, vol. 83, no. 3, pp. 434-439, 2006.

[59]

M. von Haartman, G. Malm and M. Östling, "Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate," IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 836-846, 2006.

[60]

T. Johansson et al., "Influence of SOI-generated stress on BiCMOS performance," Solid-State Electronics, vol. 50, no. 6, pp. 935-942, 2006.

[61]

B. G. Malm et al., "Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base," IEEE Electron Device Letters, vol. 26, no. 4, pp. 246-248, 2005.

[62]

J. Seger et al., "Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator," Applied Physics Letters, vol. 86, no. 25, 2005.

[63]

M. von Haartman et al., "Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics," Solid-State Electronics, vol. 49, no. 6, pp. 907-914, 2005.

[64]

E. Haralson et al., "NiSi integration in a non-selective base SiGeCHBT process," Materials Science in Semiconductor Processing, vol. 8, no. 03-jan, pp. 245-248, 2005.

[65]

B. G. Malm et al., "Self-heating effects in a BiCMOS on SOI technology for RFIC applications," IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1423-1428, 2005.

[66]

E. Suvar et al., "Characterization of leakage current related to a selectively grown collector in SiGeC heterojunction bipolar transistor structure," Applied Surface Science, vol. 224, no. 1-4, pp. 336-340, 2004.

[67]

E. Haralson, B. G. Malm and M. Östling, "Device design for a raised extrinsic base SiGe bipolar technology," Solid-State Electronics, vol. 48, no. 11-okt, pp. 1927-1931, 2004.

[68]

S. Erdal et al., "High frequency performance of SiGeCHBTs with selectively & non-selectively grown collector," Physica Scripta, vol. T114, pp. 138-141, 2004.

[69]

M. von Haartman et al., "Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics," Solid-State Electronics, vol. 48, no. 12, pp. 2271-2275, 2004.

[70]

E. Haralson et al., "The effect of C on emitter-base design for a single-polysilicon SiGe : C HBT with an IDP emitter," Applied Surface Science, vol. 224, no. 1-4, pp. 330-335, 2004.

[71]

M. von Haartman et al., "1/f noise in Si and Si0.7Ge0.3 pMOSFETs," IEEE Transactions on Electron Devices, vol. 50, pp. 2513-2519, 2003.

[72]

B. G. Malm and M. Östling, "Ge-profile design for improved linearity of SiGe double HBTs," IEEE Electron Device Letters, vol. 23, no. 1, pp. 19-21, 2002.

[73]

B. G. Malm and M. Östling, "Mixed mode circuit and device simulation of RF harmonic distortion for high-speed SiGeHBTs," Solid-State Electronics, vol. 46, no. 10, pp. 1567-1571, 2002.

[74]

B. G. Malm et al., "Implanted collector profile optimization in a SiGeHBT process," Solid-State Electronics, vol. 45, no. 3, pp. 399-404, 2001.

[75]

M. Sanden et al., "Lateral base design rules for optimized low-frequency noise of differentially grown SiGe heterojunction bipolar transistors," Microelectronics and reliability, vol. 41, no. 6, pp. 881-886, 2001.

[76]

J. V. Grahn et al., "A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget," Solid-State Electronics, vol. 44, no. 3, pp. 549-554, 2000.

[77]

M. Sanden et al., "Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors," Microelectronics and reliability, vol. 40, no. 11, pp. 1863-1867, 2000.

[78]

B. G. Malm, J. V. Grahn and M. Östling, "Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGeHBT DC and HF characteristics," Solid-State Electronics, vol. 44, no. 10, pp. 1747-1752, 2000.

Konferensbidrag

[79]

B. G. Malm and G. Hamrin, "Citation Practices in Final Year Computer Science and Electrical Engineering Bachelor Theses," in Proceedings - 2022 IEEE International Conference on Teaching, Assessment and Learning for Engineering, TALE 2022, 2022, pp. 65-70.

[80]

M. Ekström, B. G. Malm and C.-M. Zetterling, "Ultrafast Pulsed I-V and Charge Pumping Interface Characterization of Low Voltage n-Channel SiC MOSFETs," in Silicon Carbide and Related Materials 2019, 2020, pp. 642-651.

[81]

B. G. Malm, "Fact or Fiction? – Citation Categories and their Use Cases in Thesis Bibliographies at KTH," in This work was presented at KTH Scholarship of teaching and learning (SoTL) March 29, 2019, 2019.

[82]

M. W. Hussain et al., "Silicon carbide BJT oscillator design using S-parameters," in Silicon Carbide and Related Materials 2018, 2019, pp. 674-678.

[83]

A. Abedin et al., "GOI fabrication for monolithic 3D integration," in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, 2018, pp. 1-3.

[84]

M. W. Hussain et al., "Silicon Carbide BJT Oscillator Design Using S-Parameters," in European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018.

[85]

B. G. Malm et al., "Gated base structure for improved current gain in SiC bipolar technology," in 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, 2017, pp. 122-125.

[86]

S. Banuazizi et al., "Order of magnitude improvement of nano-contact spin torque nano-oscillator performance," in 2017 IEEE International Magnetics Conference, INTERMAG 2017, 2017.

[87]

S. S. Suvanam et al., "Total Dose Effects on 4H-SiC Bipolar Junction Transistors," in European Conference on Silicon Carbide and Related Materials 2016 (ECSCRM-16), 2017.

[88]

A. Salemi et al., "Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance," in 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), 2015, pp. 249-252.

[89]

A. Salemi et al., "Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes," in Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 2015, pp. 269-272.

[90]

M. Olyaei et al., "Improved Low-frequency Noise for 0.3nm EOT Thulium Silicate Interfacial Layer," in Solid State Device Research Conference (ESSDERC), 2014 44th European, 2014, pp. 361-364.

[91]

M. M. Naiini et al., "Integrating 3D PIN germanium detectors with high-k ALD fabricated slot waveguides," in ULIS 2014 - 2014 15th International Conference on Ultimate Integration on Silicon, 2014, pp. 45-48.

[92]

M. Olyaei et al., "A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer," in 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013, 2013, pp. 1-4.

[93]

S. S. Suvanam et al., "Effects of 3 MeV protons on 4H-SiC bipolar devices and integrated OR-NOR gates," in Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 2013.

[94]

M. Naiini et al., "Low loss high-k slot waveguides for silicon photonics," in Dev. Res. Conf. Conf. Dig., 2013, pp. 95-96.

[95]

A. J. Eklund et al., "Triple mode-jumping in a spin torque oscillator," in 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013, 2013, p. 6578965.

[96]

M. Östling et al., "Atomic layer deposition-based interface engineering for high-k/metal gate stacks," in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012, p. 6467643.

[97]

M. M. Naiini et al., "CMOS compatible ALD high-k double slot grating couplers for on-chip optical interconnects," in Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, 2012, pp. 93-96.

[98]

M. M. Naiini et al., "Double slot high-k waveguide grating couplers for silicon photonics," in Device Research Conference (DRC), 2012 70th Annual, 2012, pp. 69-70.

[99]

A. C. Fischer et al., "Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching," in 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012, 2012, pp. 1-4.

[100]

G. Malm et al., "Quantum Mechanical TCAD Study of Epitaxial SiGe Thermistor Layers," in International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2012, pp. 173-176.

[101]

A. Eklund et al., "1/f and white frequency noise in a synchronized spin torque oscillator pair," in 56th Annual Conference on Magnetism and Magnetic Materials, 2011, pp. 504-504.

[102]

M. Naiini et al., "ALD high-k layer grating couplers for single and double slot on-chip SOI photonics," in 41st European Solid-State Device Research Conference, ESSDERC 2011, 2011, pp. 191-194.

[103]

L. Lanni et al., "Bipolar Integrated OR-NOR Gate in 4H-SiC," in Proceedings of International Conference on Silicon Carbibe and Related Materials 2011, 2011.

[104]

M. Naiini, G. Malm and M. Östling, "Fully etched grating couplers for atomic layer deposited horizontal slot waveguides," in 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, 2011, pp. 126-129.

[105]

C.-M. Zetterling et al., "Future high temperature applications for SiC integrated circuits," in 16th Semiconducting and Insulating Materials Conference (SIMC-XVI), Stockholm, Sweden, June 19-23, 2011, 2011.

[106]

M. Olyaei et al., "Low-frequency Noise in High-k LaLuO₃/TiN MOSFETs," in 2011 International Semiconductor Device Research Symposium (ISDRS), 2011, pp. TA01-TA04.

[107]

G. Malm, M. Olyaei and M. Östling, "Low-frequency noise in FinFETs with PtSi Schottky-barrier source/drain contacts," in Proceedings of the IEEE 21st International Conference on Noise and Fluctuations, ICNF 2011, 2011, pp. 135-138.

[108]

L. Donetti et al., "On the effective mass of holes in inversion layers," in International Conference on Ultimate Integration on Silicon, 2011, pp. 50-53.

[109]

M. Östling et al., "SiC Bipolar Devices for High Power and Integrated Drivers," in Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE, 2011, pp. 227-234.

[110]

M. Östling et al., "Silicon carbide bipolar power devices," in ECS Transactions, 2011, pp. 189-200.

[111]

M. Östling et al., "Technology challenges in silicon devices beyond the 16 nm node," in Proceedings of the 18th International Conference : Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 2011, pp. 27-31.

[112]

L. Farese et al., "Experimental Study of Degradation in 4H-SiC BJTs by Means of Electrical Characterization and Electroluminescence," in SILICON CARBIDE AND RELATED MATERIALS 2009, 2010, pp. 1037-1040.

[113]

M. Östling et al., "Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology," in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2010, pp. 41-45.

[114]

M. Östling et al., "Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts," in 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, pp. 9-13.

[115]

B. G. Malm et al., "Comprehensive temperature modeling of strained epitaxial silicon-germanium alloy thermistors," in 2009 International Semiconductor Device Research Symposium, ISDRS '09, 2009, p. 5378337.

[116]

L. Di Benedetto et al., "Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers," in ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, 2009, pp. 101-104.

[117]

S. Persson et al., "Fabrication and characterisation of strained Si heterojunction bipolar transistors on virtual substrates," in IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, pp. 735-738.

[118]

B. G. Malm et al., "Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates," in SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES : MATERIALS, PROCESSING, AND DEVICES, 2008, pp. 529-537.

[119]

M. Östling et al., "Towards Schottky-Barrier Source/Drain MOSFETs," in 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, pp. 146-149.

[120]

M. Östling et al., "Critical technology issues for deca-nanometer MOSFETs," in ICSICT-2006 : 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2007, pp. 27-30.

[121]

B. G. Malm, M. von Haartman and M. Östling, "Influence of dislocations on low frequency noise in nMOSFETs fabricated on tensile strained virtual substrates," in Noise and Fluctuations, 2007, pp. 133-136.

[122]

J. Hållstedt et al., "Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates," in ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008, 2007, pp. 319-322.

[123]

M. Östling et al., "Device integration issues towards 10 nm MOSFETs," in 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2006, pp. 25-30.

[124]

A. Berrier et al., "Electrical conduction through a 2D InP-based photonic crystal - art. no. 63220J," in Tuning the Optic Response of Photonic Bandgap Structures III, 2006, pp. J3220-J3220.

[125]

T. Johansson et al., "Influence of SOI-generated stress on BiCMOS performance," in Semiconductor Device Research Symposium, 2005 International, 2005, pp. 444-445.

[126]

M. von Haartman et al., "Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain," in Noise and Fluctuations, 2005, pp. 307-310.

[127]

G. Malm and M. Östling, "Network analyzer measurements and physically based analysis of amplitude and phase distortion in SiGeC HBTs," in 2005 International Semiconductor Device Research Symposium, 2005, pp. 74-75.

[128]

M. von Haartman et al., "Noise in Si and SiGe MOSFETs with high-k gate dielectrics," in Noise and Fluctuations, 2005, pp. 225-230.

[129]

M. Östling et al., "Novel integration concepts for sige-based rf-MOSFETs," in Proc. Electrochem. Soc., 2005, pp. 270-284.

[130]

E. Haralson et al., "HRXRD analysis of SiGeC layers for BiCMOS applications," in SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium, 3 October 2004 through 8 October 2004, Honolulu, HI, United States, 2004, pp. 135-142.

[131]

M. Östling, E. Haralson and G. Malm, "High performance SiGeC HBT technology for radio frequency applications," in 2004 Asia-Pacific Radio Science Conference - Proceedings, 2004, pp. 480-483.

[132]

E. Haralson et al., "Influence of self heating in a BiCMOS on SOI technology," in ESSCIRC 2004 : Proceedings of the 34th European Solid-State Device Research Conference, 2004, pp. 337-340.

Icke refereegranskade

Artiklar

[133]

M. Östling and B. G. Malm, "SELECTED PAPERS FROM THE ESSDERC 2011 CONFERENCE Foreword," Solid-State Electronics, vol. 74, pp. 1-1, 2012.

Konferensbidrag

[134]

B. G. Malm, A. Eklund and M. Dvornik, "Micromagnetic Modeling of Telegraphic Mode Jumping in Microwave Spin Torque Oscillators," in 25th International Conference on Noise and Fluctuations – ICNF 2019, 2019.

[135]

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