This course is based on the most important component of all integrated circuits, the MOSFET transistor, which is made of silicon with nanometer dimensions. The focus is on low-power CMOS technology. New topologies and manufacturing methods are discussed according to Moore's Law. The course also provides a foundation in silicon-based memory technologies and new alternative technologies based on other physical principles and materials. Components with particularly high performance for e.g. high frequency applications are also introduced with examples from III/V-semiconductor technology or equivalent.

Course contents:

• Basic physics for the MOS system and formulation of approximate voltage-current relations for the MOS transistor. Compact physics models for circuit simulation. Modelling of extreme cases in the fabrication process, e.g. process corners.
• Scaling theory and CMOS technology nodes.
• Modern CMOS device topologies, SOI and FinFET, 3D structures including nanowire/sheet.
• Memory technologies: charge-based, resistive or based on other physical
• principles.
• New technologies and applications such as spintronics, 2D materials and 3D fabrication methods.
• Design rules, robustness, testing, reliability, failure analysis, variability at component, chip and wafer level.
• Material properties and transport characteristics in III/V and other compound high mobility semiconductors.

After passing the course, the student should be able to

• describe properties and limitations of a MOSFET transistor in an advanced CMOS technology node
• give examples of components and materials suitable for replacing or complementing silicon-based CMOS and justify the need for new component and circuit topologies beyond CMOS including 3D fabrication methods
• describe the features, characteristics and limitations of the most common types of integrated charge-coupled memories in silicon technology
• give examples of components and materials that are appropriate to replace or complement silicon-based CMOS or charge-coupled memories, for example for low supply voltages or low power applications
• use physical and compact modelling to design components with desirable properties equivalent to a future technology node
• describe the properties and limitations of high performance devices, such as HBT (heterojunction bipolar transistor), HEMT (high-electron-mobility-transistor) or MODFET in silicon-, III/V- or compound-semiconductors together with relevant material and device physics.

This course is lecture based with 1 lab and some numerical home assignments

No information inserted

Students at KTH with a permanent disability can get support during studies from Funka:

Funka - compensatory support for students with disabilities

• LAB1 - Computer and experimental laboratory work, 3.0 credits, grading scale: P, F
• TEN1 - Written exam, 4.5 credits, grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

If the course is discontinued, students may request to be examined during the following two academic years.

• All members of a group are responsible for the group's work.
• In any assessment, every student shall honestly disclose any help received and sources used.
• In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.