In this course, we review the process technologies used to build integrated circuits. You will learn basic and advanced techniques to define patterns, add and remove materials on substrates. Both state-of-the-art high volume techiniques as well as technologies used in R&D are covered in the course. In the lab, we will build functional CMOS circuits from scratch using SOI wafers as starting material.
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Content and learning outcomes
The course covers process technologies that are used in micro- and nanofabrication of devices and systems on wafers. Applications include all technologies that are based on wafer scale fabrication such as integrated circuits, micro-electro-mechanical systems and optical devices. The basic unit processes deposition, patterning, etching, doping and heat treatment are covered, followed by process integration to build complex devices including statistical process control and yield models. Moore's law and the basic economics for integrated circuits are covered and examplified by reviewing the state-of-the art process technology nodes. Hands-on experience of fabricating devices in a clean room (Electrum Laboratory) and use a number of unit processes included in the course.
The course gives the student basic understanding of the sustainability aspects in integrated circuit fabrication.
Intended learning outcomes
After the course, the student should be able to
- discuss and review unit manufacturing processes for micro- and nanofabrication on wafers
- discuss and review Moore's law and advanced process technologies
- discuss and review examples of process integration
- use models and calculate relevant characteristics and conditions in process technology
- fabricate devices in a clean room.
Literature and preparations
Knowledge in calculus in one variable, 7,5 credits, corresponding to completed course SF1625/SF1673/SF1685.
Knowledge in classical physics, 7,5 credits, corresponding to completed course SK1108/SK1118.
Documented knowledge in English corresponding to the upper secondary course English B/English 6.
Courses on BSc level or higher in solid-state physics and semiconductor devices.
Examination and completion
If the course is discontinued, students may request to be examined during the following two academic years.
- LAB1 - Lab, 1.0 credits, grading scale: P, F
- TENM - Oral exam, 4.0 credits, grading scale: A, B, C, D, E, FX, F
- TENS - Written exam, 2.5 credits, grading scale: A, B, C, D, E, FX, F
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
Opportunity to complete the requirements via supplementary examination
Opportunity to raise an approved grade via renewed examination
- All members of a group are responsible for the group's work.
- In any assessment, every student shall honestly disclose any help received and sources used.
- In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.
Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.Course web IH2659
Main field of study
The former module TEN1 will be replaced by TENS and TENM as of Autumn 2023.
In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.