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IH2663 Advanced Semiconductor Devices 7.5 credits

Information per course offering

Termin

Information for Spring 2026 Start 16 Mar 2026 programme students

Course location

KTH Campus

Duration
16 Mar 2026 - 1 Jun 2026
Periods
P4 (7.5 hp)
Pace of study

50%

Application code

61159

Form of study

Normal Daytime

Language of instruction

English

Course memo
Course memo is not published
Number of places

Places are not limited

Target group

Mandatory for TNTEM, but open to all programmes as long as it can be included in your programme.

Planned modular schedule
[object Object]
Schedule
Schedule is not published

Contact

Examiner
No information inserted
Course coordinator
No information inserted
Teachers
No information inserted

Course syllabus as PDF

Please note: all information from the Course syllabus is available on this page in an accessible format.

Course syllabus IH2663 (Spring 2026–)
Headings with content from the Course syllabus IH2663 (Spring 2026–) are denoted with an asterisk ( )

Content and learning outcomes

Course contents

This course is based on the most important component of all integrated circuits, the MOSFET transistor, which is made of silicon with nanometer dimensions. The focus is on low-power CMOS technology. New topologies and manufacturing methods are discussed according to Moore's Law. The course also provides a foundation in silicon-based memory technologies and new alternative technologies based on other physical principles and materials. Components with particularly high performance for e.g. high frequency applications are also introduced with examples from III/V-semiconductor technology or equivalent.

Course contents:

  • Basic physics for the MOS system and formulation of approximate voltage-current relations for the MOS transistor. Compact physics models for circuit simulation. Modelling of extreme cases in the fabrication process, e.g. process corners.
  • Scaling theory and CMOS technology nodes.
  • Modern CMOS device topologies, SOI and FinFET, 3D structures including nanowire/sheet.
  • Memory technologies: charge-based, resistive or based on other physical
  • principles.
  • New technologies and applications such as spintronics, 2D materials and 3D fabrication methods.
  • Design rules, robustness, testing, reliability, failure analysis, variability at component, chip and wafer level.
  • Material properties and transport characteristics in III/V and other compound high mobility semiconductors.

Intended learning outcomes

After passing the course, the student should be able to

  • describe properties and limitations of a MOSFET transistor in an advanced CMOS technology node
  • give examples of components and materials suitable for replacing or complementing silicon-based CMOS and justify the need for new component and circuit topologies beyond CMOS including 3D fabrication methods
  • describe the features, characteristics and limitations of the most common types of integrated charge-coupled memories in silicon technology
  • give examples of components and materials that are appropriate to replace or complement silicon-based CMOS or charge-coupled memories, for example for low supply voltages or low power applications
  • use physical and compact modelling to design components with desirable properties equivalent to a future technology node
  • describe the properties and limitations of high performance devices, such as HBT (heterojunction bipolar transistor), HEMT (high-electron-mobility-transistor) or MODFET in silicon-, III/V- or compound-semiconductors together with relevant material and device physics.

Literature and preparations

Specific prerequisites

Knowledge of the function and use of semiconductor components corresponding to 7.5 higher education credits, equivalent to completed course IL2240.

Active participation in a second-cycle course offering where the final examination is not yet reported in LADOK is considered equivalent to completion of the course.
Being registered for a course counts as active participation.
The term 'final examination' encompasses both the regular examination and the first re-examination.

Literature

You can find information about course literature either in the course memo for the course offering or in the course room in Canvas.

Examination and completion

If the course is discontinued, students may request to be examined during the following two academic years.

Grading scale

A, B, C, D, E, FX, F

Examination

  • LAB1 - Computer and experimental laboratory work, 3.0 credits, grading scale: P, F
  • TEN1 - Written exam, 4.5 credits, grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Examiner

No information inserted

Ethical approach

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Further information

Course room in Canvas

Registered students find further information about the implementation of the course in the course room in Canvas. A link to the course room can be found under the tab Studies in the Personal menu at the start of the course.

Offered by

Main field of study

Electrical Engineering

Education cycle

Second cycle

Supplementary information

In this course, the EECS code of honor applies, see:
http://www.kth.se/en/eecs/utbildning/hederskodex