IL2217 Digital Design with HDL 7.5 credits

Digital konstruktion med HDL

  • Education cycle

    Second cycle
  • Main field of study

  • Grading scale

    A, B, C, D, E, FX, F

Course offerings

Autumn 18 for programme students

Intended learning outcomes

After the course the student shall be able to:

  • model digital hardware using a hardware description language
  • name and describe the different phases of the design flow for digital hardware
  • point out the synthesizable subset of a hardware description language
  • name different hardware description languages
  • describe different types of target architectures for digital hardware
  • design digital hardware for FPGAs
  • explain the principle functionality of a hardware description language that models both analog and digital hardware
  • use typical design techniques for combinational circuits, asynchronous and synchronous state machines and busses.

Course main content

  • Introduction to techniques for system design and implementation
  • Introduction to hardware description languages
  • Modeling systems with VHDL
  • Synthesizable subset of VHDL
  • Alternatives to VHDL
  • Introduction to VHDL-AMS (Analog and mixed-signal VHDL)
  • Design and analysis of combinational and sequential components
  • Target architectures
  • FPGA synthesis
  • Asynchronous versus synchronous state machines
  • Microcontrollers and databusses

Eligibility

The course requires good knowledge of digital design, corresponding to IE1204 Digital Design and basic knowledge about computer architecture, corresponding to IS1200 Computer Hardware Engineering.

Literature

Kursboken meddelas en månad innan kursstart på kurswebsidan.

Examination

  • LAB1 - Laboratory Work, 4.5, grading scale: P, F
  • TEN1 - Examination, 3.0, grading scale: A, B, C, D, E, FX, F

Grading scale: A/B/C/D/E/Fx/F

Requirements for final grade

  • Written exam, 3.0 hp (TEN1: Grade A-F)
  • Laboratory course, 4.5 hp (LAB1: Grade P, F) 

The grade of the written exam (TEN1) is also the final grade of the course.  

The lab course must be completed during the study year. If the course is not completed during the study year old laboratories are not counted anymore.  

Offered by

EECS/Electronics

Contact

Johnny Öberg (johnnyob@kth.se)

Examiner

Johnny Öberg <johnnyob@kth.se>

Version

Course syllabus valid from: Autumn 2008.
Examination information valid from: Spring 2019.