IL2225 Embedded Hardware Design in ASIC and FPGA 7.5 credits

• Essential concepts for logic/FSM and Algorithm implementation using automated design flows.
• Use of HDL coding styles for efficiency, simulation, timing, clock domain crossing and power and cogestion concious.
• Constraints of Technology and Optimisation and interace to foundary and back end physical synthesis flow.
• Optimizing Designs for area, performance and power in Logic/FSM synthesis.
• Static Timing Analysis.
• High Level Synthesis concepts and design flow.
• Synthesis for Scheduling, Allocation, Binding, Storage, Interconnect and Controller Synthesis.
• Hardware accelerators.

On completion of the course, the students should be able to

• explain the concepts of Abstraction, Domain, Synthesis and Analysis and classification of Synthesis Tools
• explain implementation methods such as Full Custom, Std Cells, Mask Programmable Gate Arrays and FPGA and comparison between them
• use logic/FSM coding styles and Algorithms in HCD for efficient implementation and reuse
• account for the logic/FSM architectural design space and meaning of the HDL code
• optimize Area, Performance and Power with respect to logic/FSM on algorithmic level
• account for the limitations of Technology and Optimization, their implications and use in logic/FSM
• describe the libraries used in Logic Synthesis
• calculate and analyze performance and power for logic/FSM at the algorithmic level
• explain methods for Logic Synthesis and place-and-route

Knowledge in electrical circuit analysis, 6 credits, corresponding to completed course EI1110/EI1120/IE1206.

Knowledge in digital design, 6 credits, corresponding to completed course IE1205.

Knowledge in digital design and validation using hardware description languages, including experience with HDL simulators such as ModelSim or Xcelium, 6 credits, corresponding to completed course IL2203.

• Basic experience in Linux environments
• Basic programming and scripting knowledge
• Basic usage of the command line

The tools used in the labs run exclusively on KTH servers. The laboratories can be done either using KTH computers or personal ones by connecting to the servers using SSH. To access the course software tools from outside KTH premises an internet connection and KTH VPN is required.

If the course is discontinued, students may request to be examined during the following two academic years.

• PROA - Project work, 4.5 credits, grading scale: A, B, C, D, E, FX, F
• TENH - Oral exam, - credits, grading scale: A, B, C, D, E, FX, F
• TENQ - Quiz, 3.0 credits, grading scale: P, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

TENQ and PROA can give a maximum final grade of C. TENH is a voluntary oral examination for a higher final grade.

Ahmed Hemani

• All members of a group are responsible for the group's work.
• In any assessment, every student shall honestly disclose any help received and sources used.
• In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Students who have started the course with the modules TEN1 and LAB1 will be allowed to be examined on these to complete the course up to and including 2025-06-10.

The HEMA module has been replaced by TENQ and the TENA module has been replaced by TENH.

In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.