IL2225 Embedded Hardware Design in ASIC and FPGA 7.5 credits

Hårdvarukonstruktion i ASIC och FPGA för inbyggda system

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Course information

Content and learning outcomes

Course contents *

  • Essential concepts for logic/FSM and Algorithm implementation using automated design flows.
  • Logic/FSM Synthesis Synthesis concepts and design flow.
  • HDL coding styles for efficiency, simulation, timing, clock domain crossing and power and cogestion concious.
  • Technology and Optimisation Constraints and interace to foundary and back end physical synthesis flow.
  • Optimizing Designs for area, performance and power in Logic/FSM synthesis.
  • Static Timing Analysis.
  • High Level Synthesis concepts and design flow.
  • Scheduling, Allocation, Binding, Storage, Interconnect and Controller Synthesis.
  • Hardware accelerators.
  • Design Space Exploration.

Intended learning outcomes *

In this course students learn the logic/FSM and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs. The implementation methodology will be based on logic and high-level synthesis.This course will focus on logic and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs.

After taking this course, students are expected to know:

  • Concepts of Abstraction, Domain, Synthesis and Analysis and classification of Synthesis Tools.
  • Implementation styles like Full Custom, Std Cells, Mask Programmable Gate Arrays and FPGA and comparison between them.
  • Coding styles for logic/FSM and Algorithms in HDL/C for efficient implementation and reuse.
  • An understanding of the architectural space that the logic/FSM and high-level synthesis tools consider and infer from the HDL/C code.
  • Area, Performance and Power optimisation options at logic/FSM and Algorithmic Level.
  • Technology and Optimisation constraints, their implications and use in logic/FSM and High Level Synthesis.
  • Libraries used in logic/FSM and High Level Synthesis.
  • Links to Physical Design space and estimating the implications of physical design while doing logic/FSM and Algorithmic Design.
  • Methods and concepts used to estimate/analyze the performance and power at logic/FSM and algorithmic level.
  • Hardware / Software Partitioning using accelerators.
  • Logic/FSM and High-Level Synthesis methodology.

Course Disposition

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Literature and preparations

Specific prerequisites *

120 university credits (hp) in engineering or natural sciences and documented proficiency in English corresponding to English A.

Recommended prerequisites

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Equipment

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Literature

Principles of VLSI RTL Design by Sanjay Churiwala and Sapan Garg, Published by Springer + Lecture notes.

Examination and completion

Grading scale *

A, B, C, D, E, FX, F

Examination *

  • LAB1 - Laboratory Work, 3.0 credits, Grading scale: P, F
  • TEN1 - Examination, 4.5 credits, Grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Other requirements for final grade *

  • Written examination, TEN1 (4,5 credits, A-F)
  • Laboratory work, LAB1 (3,0 credits, P/F)

Opportunity to complete the requirements via supplementary examination

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Opportunity to raise an approved grade via renewed examination

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Examiner

Ahmed Hemani

Further information

Course web

Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.

Course web IL2225

Offered by

EECS/Electronics and Embedded Systems

Main field of study *

Electrical Engineering

Education cycle *

Second cycle

Add-on studies

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Contact

Ahmed Hemani (hemani@kth.se)

Ethical approach *

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Supplementary information

In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.