IL2225 Embedded Hardware Design in ASIC and FPGA 7.5 credits

Hårdvarukonstruktion i ASIC och FPGA för inbyggda system

  • Education cycle

    Second cycle
  • Main field of study

    Electrical Engineering
  • Grading scale

    A, B, C, D, E, FX, F

Course offerings

Autumn 18 for programme students

Autumn 18 Doktorand for single courses students - To application

  • Periods

    Autumn 18 P2 (7.5 credits)

  • Application code

    10122

  • Start date

    29/10/2018

  • End date

    14/01/2019

  • Language of instruction

    English

  • Campus

    KTH Kista

  • Tutoring time

    Daytime

  • Form of study

    Normal

  • Number of places *

    1 - 1

    *) The Course date may be cancelled if number of admitted are less than minimum of places. If there are more applicants than number of places selection will be made.

  • Course responsible

    Ahmed Hemani <hemani@kth.se>

  • Teacher

    Ahmed Hemani <hemani@kth.se>

    Johnny Öberg <johnnyob@kth.se>

  • Target group

    For doctoral students at KTH

  • Application

    Apply for this course at antagning.se through this application link.
    Please note that you need to log in at antagning.se to finalize your application.

Intended learning outcomes

In this course students learn the logic/FSM and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs. The implementation methodology will be based on logic and high-level synthesis.This course will focus on logic and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs.

After taking this course, students are expected to know:

  • Concepts of Abstraction, Domain, Synthesis and Analysis and classification of Synthesis Tools.
  • Implementation styles like Full Custom, Std Cells, Mask Programmable Gate Arrays and FPGA and comparison between them.
  • Coding styles for logic/FSM and Algorithms in HDL/C for efficient implementation and reuse.
  • An understanding of the architectural space that the logic/FSM and high-level synthesis tools consider and infer from the HDL/C code.
  • Area, Performance and Power optimisation options at logic/FSM and Algorithmic Level.
  • Technology and Optimisation constraints, their implications and use in logic/FSM and High Level Synthesis.
  • Libraries used in logic/FSM and High Level Synthesis.
  • Links to Physical Design space and estimating the implications of physical design while doing logic/FSM and Algorithmic Design.
  • Methods and concepts used to estimate/analyze the performance and power at logic/FSM and algorithmic level.
  • Hardware / Software Partitioning using accelerators.
  • Logic/FSM and High-Level Synthesis methodology.

Course main content

  • Essential concepts for logic/FSM and Algorithm implementation using automated design flows.
  • Logic/FSM Synthesis Synthesis concepts and design flow.
  • HDL coding styles for efficiency, simulation, timing, clock domain crossing and power and cogestion concious.
  • Technology and Optimisation Constraints and interace to foundary and back end physical synthesis flow.
  • Optimizing Designs for area, performance and power in Logic/FSM synthesis.
  • Static Timing Analysis.
  • High Level Synthesis concepts and design flow.
  • Scheduling, Allocation, Binding, Storage, Interconnect and Controller Synthesis.
  • Hardware accelerators.
  • Design Space Exploration.

Eligibility

120 university credits (hp) in engineering or natural sciences and documented proficiency in English corresponding to English A.

Literature

Principles of VLSI RTL Design by Sanjay Churiwala and Sapan Garg, Published by Springer + Lecture notes.

Examination

  • LAB1 - Laboratory Work, 3.0, grading scale: P, F
  • TEN1 - Examination, 4.5, grading scale: A, B, C, D, E, FX, F

Requirements for final grade

  • Written examination, TEN1 (4,5 credits, A-F)
  • Laboratory work, LAB1 (3,0 credits, P/F)

Offered by

ICT/Electronics

Contact

Ahmed Hemani (hemani@kth.se)

Examiner

Ahmed Hemani <hemani@kth.se>

Version

Course syllabus valid from: Autumn 2012.
Examination information valid from: Autumn 2012.