IL2225 Embedded Hardware Design in ASIC and FPGA 7.5 credits

• Essential concepts for logic/FSM and Algorithm implementation using automated design flows.
• Logic/FSM Synthesis Synthesis concepts and design flow.
• HDL coding styles for efficiency, simulation, timing, clock domain crossing and power and cogestion concious.
• Technology and Optimisation Constraints and interace to foundary and back end physical synthesis flow.
• Optimizing Designs for area, performance and power in Logic/FSM synthesis.
• Static Timing Analysis.
• High Level Synthesis concepts and design flow.
• Scheduling, Allocation, Binding, Storage, Interconnect and Controller Synthesis.
• Hardware accelerators.
• Design Space Exploration.

In this course students learn the logic/FSM and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs. The implementation methodology will be based on logic and high-level synthesis.This course will focus on logic and algorithm implementation as Embedded Hardware in a SOC Architecture realized as ASICs or FPGAs.

After taking this course, students are expected to know:

• Concepts of Abstraction, Domain, Synthesis and Analysis and classification of Synthesis Tools.
• Implementation styles like Full Custom, Std Cells, Mask Programmable Gate Arrays and FPGA and comparison between them.
• Coding styles for logic/FSM and Algorithms in HDL/C for efficient implementation and reuse.
• An understanding of the architectural space that the logic/FSM and high-level synthesis tools consider and infer from the HDL/C code.
• Area, Performance and Power optimisation options at logic/FSM and Algorithmic Level.
• Technology and Optimisation constraints, their implications and use in logic/FSM and High Level Synthesis.
• Libraries used in logic/FSM and High Level Synthesis.
• Links to Physical Design space and estimating the implications of physical design while doing logic/FSM and Algorithmic Design.
• Methods and concepts used to estimate/analyze the performance and power at logic/FSM and algorithmic level.
• Hardware / Software Partitioning using accelerators.
• Logic/FSM and High-Level Synthesis methodology.

Knowledge in electrical circuit analysis, 6 credits, corresponding to completed course EI1110/EI1120/IE1206.

Knowledge in digital design, 6 credits, corresponding to completed course IE1205.

Knowledge in digital design and validation using hardware description languages, including experience with HDL simulators such as ModelSim or Xcelium, 6 credits, corresponding to completed course IL2203.

• Basic experience in Linux environments
• Basic programming and scripting knowledge
• Basic usage of the command line

The tools used in the labs run exclusively on KTH servers. The laboratories can be done either using KTH computers or personal ones by connecting to the servers using SSH. To access the course software tools from outside KTH premises an internet connection and KTH VPN is required.

If the course is discontinued, students may request to be examined during the following two academic years.

• HEMA - Homework exercises, 1.0 credits, grading scale: P, F
• PROA - Project work, 4.5 credits, grading scale: A, B, C, D, E, FX, F
• TENA - Oral examination, 2.0 credits, grading scale: P, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Ahmed Hemani

• All members of a group are responsible for the group's work.
• In any assessment, every student shall honestly disclose any help received and sources used.
• In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.

Students who have started the course with the modules TEN1 and LAB1 will be allowed to be examined on these to complete the course.

In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.