IL2452 System Design Languages 7.5 credits

Språk för system design

Please note

The information on this page is based on a course syllabus that is not yet valid.

This course introduces system-level design languages. The main content is SystemC that is a language built in C++ that spans design and verification from concept to implementation in hardware and software. SystemC is the language proposed for Electronic System-Level  (ESL) modeling, design, and verification, and has been an IEEE standard. We also study transaction level modeling techniques in SystemC. A small part of the course deals with system modeling with ForSyDe. ForSyDe, which stands for Formal System Design, is another system level design language developed at KTH. 

  • Education cycle

    Second cycle
  • Main field of study

  • Grading scale

    A, B, C, D, E, FX, F

Course offerings

Autumn 18 for programme students CANCELLED

  • Periods

    Autumn 18 P1 (7.5 credits)

  • Application code

    50406

  • Start date

    27/08/2018

  • End date

    26/10/2018

  • Language of instruction

    English

  • Campus

    KTH Kista

  • Tutoring time

    Daytime

  • Form of study

    Normal

  • Number of places *

    25 - 100

    *) The Course date may be cancelled if number of admitted are less than minimum of places. If there are more applicants than number of places selection will be made.

  • Course responsible

    Zhonghai Lu <zhonghai@kth.se>

  • Teacher

    Ingo Sander <ingo@kth.se>

    Zhonghai Lu <zhonghai@kth.se>

  • Target group

    Open to all programmes.

Intended learning outcomes

After completing the course, the student shall be able to

- explain the key concepts proposed  for system-level modeling in SystemC and how C++ features are utilized in implementing these concepts

- model systems (both hardware and software) in SystemC

- explain and compare the fundamental modeling mechanisms in SystemC and other digital design languages such as VHDL and Verilog

- master the key transaction level modeling (TLM) concepts and write own models following TLM standards for high-level fast simulation

- contrast different approaches for system-level design

Course main content

 - Review of C++ basics from the SystemC perspective
- SystemC concepts: Processes, Modules, Ports, Interfaces, Channels, and SystemC data types
- SystemC simulation kernel
- TLM concepts, interfaces, channels and modeling examples
- ForSyDe methodology

Eligibility

120 university credits (hp) in engineering or natural sciences and documented proficiency in English corresponding to English A.

Recommended prerequisites

The course requires good knowledge of

  • object-oriented software programming C++
  • digital hardware design corresponding to IL2217 Digital Design with HDL

Literature

Examination

  • LABA - Laboratory Work, 4.5, grading scale: P, F
  • TEN1 - Examination, 3.0, grading scale: A, B, C, D, E, FX, F

Offered by

EECS/Electronics

Examiner

Zhonghai Lu <zhonghai@kth.se>

Version

Course syllabus valid from: Spring 2019.
Examination information valid from: Spring 2019.