This course introduces system-level design languages. The main content is SystemC that is a language built in C++ that spans design and verification from concept to implementation in hardware and software. SystemC is the language proposed for Electronic System-Level (ESL) modeling, design, and verification, and has been an IEEE standard. We also study transaction level modeling techniques in SystemC. A small part of the course deals with system modeling with ForSyDe. ForSyDe, which stands for Formal System Design, is another system level design language developed at KTH.
- Review of C++ basics from the SystemC perspective
- SystemC concepts: Processes, Modules, Ports, Interfaces, Channels, and SystemC data types
- SystemC simulation kernel
- TLM concepts, interfaces, channels and modeling examples
- ForSyDe methodology
After completing the course, the student shall be able to
- explain the key concepts proposed for system-level modeling in SystemC and how C++ features are utilized in implementing these concepts
- model systems (both hardware and software) in SystemC
- explain and compare the fundamental modeling mechanisms in SystemC and other digital design languages such as VHDL and Verilog
- master the key transaction level modeling (TLM) concepts and write own models following TLM standards for high-level fast simulation
- contrast different approaches for system-level design
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120 university credits (hp) in engineering or natural sciences and documented proficiency in English corresponding to English A.
The course requires good knowledge of
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A, B, C, D, E, FX, F
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
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Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.
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Second cycle
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