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About course

Before choosing course

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This course introduces system-level design languages. The main content is SystemC that is a language built in C++ that spans design and verification from concept to implementation in hardware and software. SystemC is the language proposed for Electronic System-Level  (ESL) modeling, design, and verification, and has been an IEEE standard. We also study transaction level modeling techniques in SystemC. A small part of the course deals with system modeling with ForSyDe. ForSyDe, which stands for Formal System Design, is another system level design language developed at KTH. 

Course offering missing for current semester as well as for previous and coming semesters
* Retrieved from Course syllabus IL2452 (Spring 2019–)

Content and learning outcomes

Course contents

 - Review of C++ basics from the SystemC perspective
- SystemC concepts: Processes, Modules, Ports, Interfaces, Channels, and SystemC data types
- SystemC simulation kernel
- TLM concepts, interfaces, channels and modeling examples
- ForSyDe methodology

Intended learning outcomes

After completing the course, the student shall be able to

- explain the key concepts proposed  for system-level modeling in SystemC and how C++ features are utilized in implementing these concepts

- model systems (both hardware and software) in SystemC

- explain and compare the fundamental modeling mechanisms in SystemC and other digital design languages such as VHDL and Verilog

- master the key transaction level modeling (TLM) concepts and write own models following TLM standards for high-level fast simulation

- contrast different approaches for system-level design

Course Disposition

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Literature and preparations

Specific prerequisites

120 university credits (hp) in engineering or natural sciences and documented proficiency in English corresponding to English A.

Recommended prerequisites

The course requires good knowledge of

  • object-oriented software programming C++
  • digital hardware design corresponding to IL2217 Digital Design with HDL

Equipment

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Literature

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Examination and completion

If the course is discontinued, students may request to be examined during the following two academic years.

Grading scale

A, B, C, D, E, FX, F

Examination

  • LABA - Laboratory Work, 4,5 hp, betygsskala: P, F
  • TEN1 - Examination, 3,0 hp, betygsskala: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Opportunity to complete the requirements via supplementary examination

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Opportunity to raise an approved grade via renewed examination

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Examiner

Profile picture Zhonghai Lu

Ethical approach

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Further information

Course web

Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.

Course web IL2452

Offered by

EECS/Electrical Engineering

Main field of study

Computer Science and Engineering, Electrical Engineering

Education cycle

Second cycle

Add-on studies

No information inserted