Course contents *
The course presents network calculus, which is a fundamental theory for quality-of-service provision and guarantees in communication networks such as ATM and Internet, and its latest application to emerging on-chip communication networks in advanced computing devices and systems.
The course is given in the form of lectures and seminars. It consists of three modules as follows:
Module I: Network Calculus basics and its application to macro-networks (6 Lectures/seminars)
This module introduces the quality-of-service problem and the basic network calculus concepts and results. Then its application to macro-networks such as ATM and Internet is presented.
Module II: Network Calculus applied to micro-networks (4 lectures/seminars)
This module applies the knowledge in Module I, shifting the focus from macro-networks to micro-networks, i.e. networks on chip. At first, on-chip router will be introduced together with xMAS (eXecutable Micro-Architecture Specification), a latest formal communication fabric modeling framework proposed by Intel researchers. Then the NoC quality-of-service analysis methodology will be presented with case studies.
Module III: Advanced topics (2 lectures/seminars)
This module is optional. It presents advanced topics in deterministic network calculus, looking into stochastic network calculus and energy calculus.
The course content is subject to improvement reflecting latest research developments in the area.
Intended learning outcomes *
After studying the course, the students shall achieve the following learning outcomes:
- Understand the fundamental network calculus concepts and master the main results of network calculus;
- Be able to apply the theory to solve defined analytic problems in finding delay, backlog, and throughput bounds in macro- and micro- networks;
- Be able to apply the concepts and methods to build proper analytical models to analyze the QoS guarantees in communication networks;
- Beyond hand derivation of closed-form formulas, be able to build simulation models in VHDL/Verilog or C++/SystemC to validate the correctness and tightness of the analytic results.