- Essential concepts for logic/FSM and Algorithm implementation using automated design flows.
- Use of HDL coding styles for efficiency, simulation, timing, clock domain crossing and power and cogestion concious.
- Constraints of Technology and Optimisation and interace to foundary and back end physical synthesis flow.
- Optimizing Designs for area, performance and power in Logic/FSM synthesis.
- Static Timing Analysis.
- High Level Synthesis concepts and design flow.
- Synthesis for Scheduling, Allocation, Binding, Storage, Interconnect and Controller Synthesis.
- Hardware accelerators.
IL2225 Embedded Hardware Design in ASIC and FPGA 7.5 credits

Information per course offering
Information for Autumn 2026 TEBSM programme students
- Course location
KTH Campus
- Duration
- 26 Oct 2026 - 11 Jan 2027
- Periods
Autumn 2026: P2 (7.5 hp)
- Pace of study
50%
- Application code
10799
- Form of study
Normal Daytime
- Language of instruction
English
- Course memo
- Course memo is not published
- Number of places
25 - 100
- Target group
- Open to all programmes as long as it can be included in your programme.
- Planned modular schedule
- [object Object]
- Schedule
- Schedule is not published
Contact
Course syllabus as PDF
Please note: all information from the Course syllabus is available on this page in an accessible format.
Course syllabus IL2225 (Autumn 2026–)Content and learning outcomes
Course contents
Intended learning outcomes
On completion of the course, the students should be able to
- explain the concepts of Abstraction, Domain, Synthesis and Analysis and classification of Synthesis Tools
- explain implementation methods such as Full Custom, Std Cells, Mask Programmable Gate Arrays and FPGA and comparison between them
- use logic/FSM coding styles and Algorithms in HCD for efficient implementation and reuse
- account for the logic/FSM architectural design space and meaning of the HDL code
- optimize Area, Performance and Power with respect to logic/FSM on algorithmic level
- account for the limitations of Technology and Optimization, their implications and use in logic/FSM
- describe the libraries used in Logic Synthesis
- calculate and analyze performance and power for logic/FSM at the algorithmic level
- explain methods for Logic Synthesis and place-and-route
Literature and preparations
Specific prerequisites
Knowledge of basic digital design, including knowledge of CMOS, 6 credits, equivalent to completed course IE1204/IE1205.
Knowledge of basic electrical circuit analysis, 6 credits, equivalent to completed course EI1110/EI1120/IE1206.
The above knowledge of basic digital design and electrical circuit analysis may also have been acquired in a completed advanced level course of at least 7.5 credits that combines digital design and electrical circuit analysis/analog electronics, equivalent to IL2246.
Knowledge of digital design and validation with hardware description languages, 6 credits, equivalent to completed course IL2234 or IL1332.
Active participation in both IL2246 and IL2234 during period 1 of the same academic year is equated with completed course. Those who are registered are expected and considered to be actively participating.
Recommended prerequisites
- Basic experience in Linux environments
- Basic programming and scripting knowledge
- Basic usage of the command line
Literature
Examination and completion
Grading scale
Examination
- PROB - Project work, 3.0 credits, grading scale: P, F
- TEND - Digital Exam, 4.5 credits, grading scale: A, B, C, D, E, FX, F
Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.
The examiner may apply another examination format when re-examining individual students.
If the course is discontinued, students may request to be examined during the following two academic years.
Examiner
Ethical approach
- All members of a group are responsible for the group's work.
- In any assessment, every student shall honestly disclose any help received and sources used.
- In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.
Further information
Course room in Canvas
Offered by
Main field of study
Education cycle
Transitional regulations
Students who started the course with the previous modules TENQ or PROA can complete these items up to and including autumn 2027.
Students who still have the previous exam component TENB will instead take TEND.
Supplementary information
In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.