IL2236 Embedded Many-Core Architectures 7.5 credits

Arkitekturer för inbyggda mångkärniga system

Intended learning outcomes

After studying the course, the students shall be able to do the following as learning outcomes:

  • Describe and compare various on-chip bus protocols and arbitration schemes.
  • Explain and apply concepts and design principles of interconnection networks in topology, routing, flow control, deadlock/livelock and quality-of-service (QoS).
  • Describe and model on-chip pipelined routers, as well as describe and compare processor-network interface designs.
  • Establish network performance evaluation setups, make qualitative and quantitative evaluation of network performance using theoretical and simulation methods.
  • Describe real-time networking principles in embedded systems, explain and compare time-triggered and event-triggered protocols in general and industrial protocols such as CAN, FlexRay and TTP in particular.
  • Explain and apply worst-case communication time analysis techniques in distributed embedded architectures.

Course main content

The course focuses on the communication problem of on-chip and off-chip many-core architectures in embedded systems. It teaches basic concepts and principles of on-chip bus and interconnection network, and presents details of on-chip router and network interface designs, network quality-of-service (QoS) provisioning and performance evaluation methodology. Moreover,  it discusses realtime networking and worst-case communication time analysis in embedded many-core architectures and introduces industrial practices such as CAN, FlexRay and TTP.

The course consists of ten lectures, and 4 exercises, one of which can be in the mini-project form. An invited lecture from industry or academia may be organized.

The lectures are structured as three modules:

Module I: Concepts and principles

This module introduces the problems in many-core systems with focus on communication architectures. Concepts  and principles of on-chip buses and interconnection networks will be presented. Particularly, network topology, routing and flow control, deadlock and livelock issues et cetera. will be investigated.

Module II: Design and evaluation

This module focuses on on-chip router and processor-network interface designs, QoS properties, and performance evaluation. The micro-architecture of a classic router will be detailed and network interfaces for both message passing and shared memory architectures will be presented. As a crucial component for network design, QoS properties of different design alternatives will be investigated. Furthermore, performance evaluation methodology will be systematically introduced.

Module III: Distributed realtime architectures

This module considers distributed many-core systems in embedded environments such as automotives and airplanes. Various media-access protocols for real-time networking will be studied. Particularly, industrial standards such as CAN, FlexRay and TTP will be introduced. Moreover, worst-case communication time analysis methods will be presented.

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Course information

Content and learning outcomes

Course contents *

The course focuses on the communication problem of on-chip and off-chip many-core architectures in embedded systems. It teaches basic concepts and principles of on-chip bus and interconnection network, and presents details of on-chip router and network interface designs, network quality-of-service (QoS) provisioning and performance evaluation methodology. Moreover,  it discusses realtime networking and worst-case communication time analysis in embedded many-core architectures and introduces industrial practices such as CAN, FlexRay and TTP.

The course consists of ten lectures, and 4 exercises, one of which can be in the mini-project form. An invited lecture from industry or academia may be organized.

The lectures are structured as three modules:

Module I: Concepts and principles

This module introduces the problems in many-core systems with focus on communication architectures. Concepts  and principles of on-chip buses and interconnection networks will be presented. Particularly, network topology, routing and flow control, deadlock and livelock issues et cetera. will be investigated.

Module II: Design and evaluation

This module focuses on on-chip router and processor-network interface designs, QoS properties, and performance evaluation. The micro-architecture of a classic router will be detailed and network interfaces for both message passing and shared memory architectures will be presented. As a crucial component for network design, QoS properties of different design alternatives will be investigated. Furthermore, performance evaluation methodology will be systematically introduced.

Module III: Distributed realtime architectures

This module considers distributed many-core systems in embedded environments such as automotives and airplanes. Various media-access protocols for real-time networking will be studied. Particularly, industrial standards such as CAN, FlexRay and TTP will be introduced. Moreover, worst-case communication time analysis methods will be presented.

Intended learning outcomes *

After studying the course, the students shall be able to do the following as learning outcomes:

  • Describe and compare various on-chip bus protocols and arbitration schemes.
  • Explain and apply concepts and design principles of interconnection networks in topology, routing, flow control, deadlock/livelock and quality-of-service (QoS).
  • Describe and model on-chip pipelined routers, as well as describe and compare processor-network interface designs.
  • Establish network performance evaluation setups, make qualitative and quantitative evaluation of network performance using theoretical and simulation methods.
  • Describe real-time networking principles in embedded systems, explain and compare time-triggered and event-triggered protocols in general and industrial protocols such as CAN, FlexRay and TTP in particular.
  • Explain and apply worst-case communication time analysis techniques in distributed embedded architectures.

Course Disposition

No information inserted

Literature and preparations

Specific prerequisites *

  • Programming skill in one design language, e.g. C/C++, Python, Java, or SystemC (IL2206 Embedded Systems or IL2452 System Design Languages).
  • Verilog/VHDL (e.g. IL2217 Digital Design with HDL).

Recommended prerequisites

No information inserted

Equipment

No information inserted

Literature

  • Willian J. Dally and Brian Towles, "Principles and Practices of Interconnection Networks". Morgan Kaufmann Publishers.
  • Hermann Kopetz. "Real-Time Systems: Design Principles for Distributed Embedded Applications". Springer.

  • Recommended manuscripts and research papers

Examination and completion

Grading scale *

A, B, C, D, E, FX, F

Examination *

  • ANN1 - Homework Exercises, 3.0 credits, Grading scale: P, F
  • TEN1 - Examination, 4.5 credits, Grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Opportunity to complete the requirements via supplementary examination

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Opportunity to raise an approved grade via renewed examination

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Examiner

Zhonghai Lu

Further information

Course web

Further information about the course can be found on the Course web at the link below. Information on the Course web will later be moved to this site.

Course web IL2236

Offered by

EECS/Electronics and Embedded Systems

Main field of study *

Electrical Engineering

Education cycle *

Second cycle

Add-on studies

No information inserted

Ethical approach *

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Supplementary information

In this course, the EECS code of honor applies, see: http://www.kth.se/en/eecs/utbildning/hederskodex.

The course is offered once per year.

Course Literature

  • Willian J. Dally and Brian Towles, "Principles and Practices of Interconnection Networks". Morgan Kaufmann Publishers.
  • Hermann Kopetz. "Real-Time Systems: Design Principles for Distributed Embedded Applications". Springer.
  • Recommended manuscripts and research papers