IS2202 Computer Systems Architecture 7.5 credits

Datorsystemarkitektur

Please note

The information on this page is based on a course syllabus that is not yet valid.

The overall objective with the course is to give knowledge and insights into the design of modern computers, in particular the processor design including parallel computational pipelines and advanced memory hierarchies.

  • Education cycle

    Second cycle
  • Main field of study

  • Grading scale

    A, B, C, D, E, FX, F

Course offerings

Spring 19 for programme students

Spring 20 for programme students

Intended learning outcomes

The overall objective with the course is to give knowledge and insights into the design of modern computers, in particular the processor design including parallel computational pipelines and advanced memory hierarchies.

The student should, for a passing grade, be able to:

  • account for the basic quantitative principles of computer design,
  • explain the design and function of microprocessors with parallel computational pipelines and dynamic scheduling of instructions,
  • explain the design and function of a memory hierarchy for the above mentioned microprocessor,
  • explain the design and function of a multi-core processor with shared address space,
  • identify and predict a program behaviour favoured by a certain microarchitecture of a processor,
  • design and implement a simple parallel program with shared memory and explain its performance on a certain processor architecture with multiple cores,
  • describe how simulation can be used to evaluate different architectural alternatives,
  • propose and motivate a modification to a processor architecture which has potential to improve performance with the same power consumption,
  • propose and motivate a modification to a processor architecture which has potential to lower the power consumption with the same performance

Course main content

  • Memory hiearchies, hardware for virtual memory management and memory protection
  • Software and hardware methods for utilizing instruction level parallelism
  • Orientation about thread level parallelism and hardware mechanisms to utilize thread level parallelism
  • Orientation about shared memory and memory coherence

Eligibility

Bachelor's degree in computer science, electrical engineering or similar where basic couses in computer engineering and programming are included. 

Recommended prerequisites

Knowledge in computer organisation corresponding to IS1200 Computer Hardware Engineering.

Literature

Kurslitteraturen fastställs senast en månad före kursstart och meddelas på kurshemsidan: http://www.ict.kth.se/courses/IS2202.

Required equipment

Access to own computer.

Examination

  • LAB1 - Laboratory Work, 3.5, grading scale: A, B, C, D, E, FX, F
  • TEN1 - Examination, 4.0, grading scale: A, B, C, D, E, FX, F

Requirements for final grade

Written exam (3,7 hp)
Laboratory exercises on own computer (3,7 hp)

The laboratory exercises may be accounted for orally or written. Peer review of written reports may occur.

The final course grade is a combination of the grade on the written exam and the laboratory exercises.

Offered by

EECS/Computational Science and Technology

Examiner

Johnny Öberg <johnnyob@kth.se>

Supplementary information

Access to own computer.

(The course is possibly not offered spring 2015)

Version

Course syllabus valid from: Spring 2019.
Examination information valid from: Spring 2019.