Publikationer av Dimitrios Stathis
Refereegranskade
Artiklar
[1]
J. Xu et al., "Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 71, no. 2, s. 627-631, 2024.
[2]
D. Stathis et al., "Clock tree generation by abutment in synchoros VLSI design," Microprocessors and microsystems, vol. 102, 2023.
[3]
N. M. Rezk et al., "MOHAQ : Multi-Objective Hardware-Aware Quantization of recurrent neural networks," Journal of systems architecture, vol. 133, 2022.
[4]
D. Pudi et al., "Methodology for Structured Data-Path Implementation in VLSI Physical Design : A Case Study," Electronics, vol. 11, no. 18, 2022.
[5]
D. Wang et al., "Mapping the BCPNN Learning Rule to a Memristor Model," Frontiers in Neuroscience, vol. 15, 2021.
[6]
Y. Yang et al., "Optimizing BCPNN Learning Rule for Memory Access," Frontiers in Neuroscience, vol. 14, 2020.
[7]
D. Stathis et al., "eBrainII : a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex," Journal of Signal Processing Systems, vol. 92, no. 11, s. 1323-1343, 2020.
Konferensbidrag
[8]
R. Kallapu et al., "DRRA-based Reconfigurable Architecture for Mixed-Radix FFT," i Proceedings of the IEEE International Conference on VLSI Design, 2023, s. 25-30.
[9]
S. A. Mirsalari et al., "Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms," i ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity, 2023.
[10]
J. Xu et al., "Optoelectronic memristor model for optical synaptic circuit of spiking neural networks," i 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023 : Proceedings, 2023.
[11]
Y. Yang, D. Stathis och A. Hemani, "Reducing the Configuration Overhead of the Distributed Two-level Control System," i PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, s. 104-107.
[12]
J. Xu et al., "A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation," i 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS, 2021.
[13]
D. Stathis et al., "Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex," i PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, s. 685-688.
[14]
D. Stathis et al., "Clock Tree Generation by Abutment in Synchoros VLSI Design," i 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, s. 1-7.
[15]
A. K. Patan et al., "Design and Implementation of Optimized Register File for Streaming Applications," i 2021 25th International Symposium on VLSI Design and Test, VDAT 2021, 2021.
[16]
U. Altayo Gonzalez, D. Stathis och A. Hemani, "Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design," i Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021, 2021, s. 61-66.
[17]
V. Ntinas et al., "Cellular automata coupled with memristor devices : A fine unconventional computing paradigm," i 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020, 2020.
[18]
G. Baccelli et al., "NACU : A Non-Linear Arithmetic Unit for Neural Networks," i PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020.
[19]
D. Stathis et al., "Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps," i 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, s. 560-567.
[20]
P. Chaourani et al., "A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors," i IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
[21]
J. Syed, A. Hemani och D. Stathis, "Can a reconfigurable architecture beat ASIC as a CNN accelerator?," i Proceedings - 2017 17th International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation, SAMOS 2017, 2018, s. 97-104.
[22]
Y. Yang et al., "RiBoSOM : Rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform," i ACM International Conference Proceeding Series, 2018, s. 105-114.
[23]
Y. Yang et al., "MTP-caffe : Memory, timing, and power aware tool for mapping CNNs to GPUs," i ACM International Conference Proceeding Series, 2017, s. 31-36.
Icke refereegranskade
Avhandlingar
[24]
D. Stathis, "Synchoros VLSI Design Style," Doktorsavhandling Stockholm : KTH Royal Institute of Technology, TRITA-EECS-AVL, 2022:30, 2022.
Rapporter
Övriga
[26]
Senaste synkning med DiVA:
2024-04-30 00:16:12