I am PhD student supervised by Roberto Guanciale, and a member of the STEP research group at TCS/KTH.
After my master in computer science at KTH, I was at RISE SICS in Kista, Sweden, for 6 months working in the PROSPER project, and then started my PhD at KTH.
During my master's thesis, at RISE SICS and the first part of my PhD, I worked on memory isolation of a network interface controller.
My future research goals concern:
- Modeling: For instance, automate construction of hardware and software models (from formal hardware and software descriptions, e.g. VHDL and binary code), thereby enabling fast generation of reliable (less bugs compared to handmade) models and analysis of detailed properties (e.g. implications of order of operations, atomicity/granularity of operations and execution time of operations).
- Analysis: For instance, identify and automate proofs of properties of hardware subcomponents that can be used to prove (safety/security/functional correctness) properties about hardware containing those subcomponents.
My main learning interests are:
- Computer hardware (design, electronics and physics).
- Computer systems software (hypervisors/OS/device drivers/compilers).
- Mathematical logic (logic/foundations of mathematics/philosophy).
- Formal analysis of computers (software and hardware; and mathematics) with interactive theorem proving (modeling and proving, including development of tools for automation).