Ten selected publications
1. David Ramos, Marie Delmas, Ruslan Ivanov, Laura Zurauskaite, Dean Evans, Susanne Almqvist, Simija Becanovic, Per-Erik Hellström, Eric Costard and Linda Höglund, "Two-step etch in n-on-p type-II superlattices for surface leakage reduction in mid-wave infrared megapixel detectors," Opto-Electronics Review, vol. 31, no. 1, 2023. doi: 10.24425/opelre.2023.144556
2. David Ramos, Marie Delmas, Ruslan Ivanov, Dean Evans, Laura Zurauskaite, , Susanne Almqvist, Simija Becanovic, Linda Höglund, Eric Costard, and Per-Erik Hellström, "Quasi-3-dimensional simulations and experimental validation of surface leakage currents in high operating temperature type-II superlattice infrared detectors," Journal of Applied Physics, vol. 132, no. 20, s. 204501, 2022. doi: 10.1063/5.0106878
3. M. Ekström, L. Zurauskaite and P. -E. Hellström, "Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS," 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021, pp. 1-4, doi: 10.1109/EuroSOI-ULIS53016.2021.9560668.
The work demonstrates that FDSOI CMOS technolgy can be tailored to allow PFET and NFET operation at operating temperature of 300 °C with low off-state leakge <1 nA/µm.
4. L. Zurauskaite, A. Abedin, P.-E. Hellström and Mikael Östling, “Si-Passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate”, ECS Transactions, 8, 387-393(2020). DOI: 10.1149/09805.0387ecst
In the paper, we describe a process to achieve interface state densities less than \(5\times10^{11} eV^{-1}cm^{-2}\) in Ge channel devices. We also determine the boundaries on the process conditions to achive such low interface state density for Ge devices.
5. S. Hou, M. Shakir, P.-E. Hellström, B. G. Malm, C.-M. Zetterling and M. Östling, “A Silicon Carbide 256 pixel UV sensor array operating at 400 °C”, IEEE Journal of Electron Devices Society, 8, 116(2020). DOI:10.1109/JEDS.2020.2966680
The paper demonstrate SiC electronics and UV sensor working at an high operating temperature of 400 °C.
6. P. Chaourani, S. Rodriguez, P.-E. Hellström, A. Rusu, “Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27, 468(2018). DOI: 10.1109/TVLSI.2018.2877132
Monolithic 3D technology is a path to increase transistor packing density when conventional scaling is not feasible. In this paper we analyzed integration schemes of inductors for analog circuits in a monolithic 3D technology.
7. A. Abedin, L. Zurauskaite, A. Asadollahi, K. Garidis, G. Jayakumar, B. G. Malm, P.-E. Hellström and M. Östling, “Germanium on Insulator Fabrication for Monolithic 3-D integration”, IEEE Journal of Electron Device Society, 6, 588(2018). DOI:10.1109/JEDS.2018.2801335
We developed process technology for monolithic 3D integration using Ge transistors and showed their performance using a maximum process temperature of 600 °C.
8. E. Dentoni Litta, P.-E. Hellström and M. Östling, ”Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal gate CMOS Technology”, IEEE Transaction on Electron Devices, 62, 934(2015). DOI: 10.1109/TED.2015.2391179
The paper describes a highly scaled gate dielectric with an equivalent oxide thickness less than 1 nm without severe degradation of the channel mobility.
9. V. Gudmundsson, P.-E. Hellström, J. Luo, J. Lu, S.-L. Zhang and M. Östling, “Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation”, IEEE Electron Device Letters 30, 541(2009). DOI:10.1109/LED.2009.2015900
The paper demonstrate a FinFET type transistor on SOI using metallic source drain to reduced source drain resistance. The nano-scaled transistors were fabricated with conventional I-line lithography using the double patterning.
10. J. Hållstedt, M. v Haartman, P.-E. Hellström, M. Östling, and H.H. Radamsson, “Hole mobility in Ultrathin Body SOI pMOSFETs with SiGe and SiGeC Channels”, IEEE Electron Device Letters 27, 466(2006). DOI:10.1109/LED.2006.874763
In the paper we showed that adding Ge in the channel material of an fully depleted SOI MOSFET boosts the mobility of p-type MOSFETs.
