My research interests are in semiconductor process technology, especially the heterogeneous integration of materials and devices with Si CMOS technology to augment integrated circuits. More specifically I have together with Ph.D. students developed a double patterning technique that we use to fabricate nanometer-sized transistors. We also study the integration of new materials such as SiGe, Ge, high-k dielectrics, and metal gates. A key objective is to develop processes, devices, and circuits for sequential 3D integration in future CMOS technologies. I lead the work on KTH's FDSOI CMOS process and circuit technology, which is the baseline for the research on the integration of new materials and devices with CMOS electronics.
I manage the Si and SiC process line in the Electrum Laboratory with responsibility for the maintenance of tools, uptime, process control, upgrades, and future tool investments.
I teach courses in electrical circuits, semiconductor devices, and process technology at the Bachelor and Master levels.
Currently, I have open positions for M.Sc. thesis projects within the areas of transparent or high operating temperature electronics based on the FDSOI CMOS technology. If you are a student interested in these areas and want to conduct experimental work in your M.Sc. thesis, you are welcome to contact me.