Per-Erik Hellström

My research interests are in semiconductor process technology, especially the heterogeneous integration of materials and devices with Si CMOS technology to augment integrated circuits. More specifically I have together with Ph.D. students developed a double patterning technique that we use to fabricate nanometer-sized transistors. We also study the integration of new materials such as SiGe, Ge, high-k dielectrics, and metal gates. A key objective is to develop processes, devices, and circuits for sequential 3D integration in future CMOS technologies. I lead the work on KTH's FDSOI CMOS process and circuit technology, which is the baseline for the research on the integration of new materials and devices with CMOS electronics.

I manage the Si and SiC process line in the Electrum Laboratory with responsibility for the maintenance of tools, uptime, process control, upgrades, and future tool investments.

I teach courses in electrical circuits, semiconductor devices, and process technology at the Bachelor's and Master's levels.

I am currently offering the following M.Sc. thesis work starting in January 2026. All thesis projects involve experimental work in the KTH Electrum Laboratory in Kista. If you are interested in any of these projects, please contact me by email, pereh@kth.se.

KTH is a part of the EU Chips Act Wide Bandgap Pilotline (https://www.wbg-pilot-line.eu/. Within this project, we offer three M.Sc. thesis projects

1.Evaluate and optimize Ion Implantation and activation process in SiC for bipolar devices. (Taken)

2.    Evaluate and optimize nitrous monoxide Rapid Thermal Processing to improve the SiC/SiO2 interface quality.

3.    Evaluate and optimize the contact process to n-type and p-type SiC.

KTH is a part of the Vinnova project Advanced Chip Technologies (https://www.advancedchiptechnologies.lu.se/), together with industry and Lund University. Within this project, we offer the following M.Sc. thesis projects

1.      Chiplet based packaging for DC/RF signals using Si interposer.
In the MSc thesis, the student will design, fabricate, and evaluate Si interposer interconnects for DC and RF signals between chiplets. The work will be conducted in close collaboration with Ericsson and will involve fabrication in KTH Electrum Laboratory.

2.    Implementation of 3 metal layer W interconnects in FDSOI CMOS for high temperature (>300 °C) operation.