My research interests are in semiconductor process technology, especially heteorogenous integration of materials and devices with Si CMOS technology to augment integrated circuits. More specifically I have together with PhD students developed a double patterning technique that we use to fabricate nanometer sized transistors. We also study integration of new materials such as SiGe, Ge, high-k dielectrics and metal gates. A key objective is to develop processes, devices and circuits for sequential 3D integration in future CMOS technologies. I mantain and develop KTH's CMOS process line that is based on FDSOI technology. KTH's CMOS technology is used for heterogenous integration of new materials and devices with CMOS electronics. I have also manange the Si and SiC process line in the Electrum Laboratory with responsibility for maintenance of tools, uptime, process control, upgrades and future tool investments.
I teach or have been teaching courses in electrical circuits, semiconductor devices and in process technology on bachelor and master level.
Currently I have open positions for M.Sc. thesis projects within the areas of transparent or high operating temperture electronics based on the FDSOI CMOS technology. If you are a student interested in these areas and wants to conduct experimental work in your M.Sc. thesis, you are welcome to contact me.
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