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Publications by Zhonghai Lu

Peer reviewed

Articles

[1]
W. Zhu et al., "Amputee Gait Phase Recognition Using Multiple GMM-HMM," IEEE Access, vol. 12, pp. 193796-193806, 2024.
[2]
W. Fan et al., "Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 71, no. 10, pp. 4521-4525, 2024.
[3]
W. Song et al., "Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data," IEEE Access, vol. 12, pp. 11850-11864, 2024.
[5]
L. Zhu et al., "A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow," IEEE design & test, vol. 40, no. 6, pp. 39-50, 2023.
[6]
Q. Liu et al., "Health warning based on 3R ECG Sample's combined features and LSTM," Computers in Biology and Medicine, vol. 162, 2023.
[7]
Y. Wang et al., "Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs," IEEE Transactions on Computers, vol. 72, no. 11, pp. 3127-3139, 2023.
[8]
Z. Lu, "PiN : Processing in Network-on-Chip," IEEE design & test, vol. 40, no. 6, pp. 30-38, 2023.
[10]
L. Cui et al., "A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 6, pp. 1971-1975, 2022.
[11]
Y. Zhang et al., "Base-2 Softmax Function : Suitability for Training and Efficient Hardware Implementation," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 69, no. 9, pp. 3605-3618, 2022.
[12]
B. Wang and Z. Lu, "Flexible and Efficient QoS Provisioning in AXI4-based Network-on-Chip Architecture," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1523-1536, 2022.
[13]
H. Chen et al., "Huicore : A Generalized Hardware Accelerator for Complicated Functions," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 69, no. 6, pp. 2463-2476, 2022.
[14]
W. Zhu et al., "Redundancy Reduction for Sensor Deployment in Prosthetic Socket : A Case Study," Sensors, vol. 22, no. 9, pp. 3103, 2022.
[15]
X. Hu and Z. Lu, "A Configurable Hardware Architecture for Runtime Application of Network Calculus," International journal of parallel programming, vol. 49, no. 5, pp. 745-760, 2021.
[16]
W. Liu et al., "DEPS : Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 66-77, 2021.
[17]
H. Chen et al., "Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 68, no. 8, pp. 3293-3304, 2021.
[18]
J. Wang et al., "Optimal Sprinting Pattern in Thermal Constrained CMPs," IEEE Transactions on Emerging Topics in Computing, 2021.
[19]
H. Chen et al., "Symmetric-Mapping LUT-Based Method and Architecture for Computing X-Y-Like Functions," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 68, no. 3, pp. 1231-1244, 2021.
[20]
Z. Qin et al., "A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 67, no. 12, pp. 3422-3426, 2020.
[22]
B. Wang and Z. Lu, "Advance Virtual Channel Reservation," IEEE Transactions on Computers, vol. 69, no. 9, pp. 1320-1334, 2020.
[23]
Q. Chen et al., "An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 28, no. 6, pp. 1540-1544, 2020.
[25]
R. Ma et al., "BlockHammer : Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2020.
[26]
B. Wang and Z. Lu, "Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture," IEEE Access, vol. 8, pp. 182663-182678, 2020.
[27]
H. Chen et al., "Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 67, no. 11, pp. 2652-2656, 2020.
[28]
Y. Yao and Z. Lu, "Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS," IEEE Transactions on Computers, vol. 69, no. 3, pp. 410-426, 2020.
[29]
S. Guo et al., "Securing IoT Space via Hardware Trojan Detection," IEEE Internet of Things Journal, vol. 7, no. 11, pp. 11115-11122, 2020.
[32]
W. Zhang, Q. Cao and Z. Lu, "Bit-Flipping Schemes Upon MLC Flash : Investigation, Implementation, and Evaluation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 4, pp. 780-784, 2019.
[33]
R. Ma et al., "RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory," IEEE Access, vol. 7, pp. 44696-44708, 2019.
[34]
Y. Zhou et al., "SCORE : A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory," ACM Transactions on Architecture and Code Optimization (TACO), vol. 15, no. 4, 2019.
[35]
G. Du et al., "SSS : Self-aware System-on-chip Using a Static-dynamic Hybrid Method," ACM Journal on Emerging Technologies in Computing Systems, vol. 15, no. 3, 2019.
[36]
S. Guo et al., "Security-Aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs," IEEE Transactions on Industrial Informatics, vol. 15, no. 10, pp. 5435-5443, 2019.
[37]
Z. Chen et al., "Toward FPGA Security in IoT : A New Detection Technique for Hardware Trojans," IEEE Internet of Things Journal, vol. 6, no. 4, pp. 7061-7068, 2019.
[38]
J. Wang et al., "A New Parallel CODEC Technique for CDMA NoCs," IEEE Transactions on Industrial Electronics, vol. 65, no. 8, pp. 6527-6537, 2018.
[39]
X. Chen et al., "A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 26, no. 10, pp. 1953-1966, 2018.
[40]
Y. -. Long, H. -. Shen and Z. Lu, "Analysis and Evaluation of Delay Bounds for Multiplexing Models Based on Network Calculus," Tien Tzu Hsueh Pao, vol. 46, no. 8, pp. 1815-1821, 2018.
[41]
Z. Wang et al., "Cache Access Fairness in 3D Mesh-Based NUCA," IEEE Access, vol. 6, pp. 42984-42996, 2018.
[42]
Q. Xiong et al., "Characterizing 3D Floating Gate NAND Flash : Observations, Analyses, and Implications," ACM Transactions on Storage, vol. 14, no. 2, 2018.
[43]
Y. Long, Z. Lu and H. Shen, "Composable Worst-Case Delay Bound Analysis Using Network Calculus," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3, pp. 705-709, 2018.
[44]
C. Li et al., "RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router," IEEE Transactions on Parallel and Distributed Systems, vol. 29, no. 9, pp. 2090-2104, 2018.
[45]
Z. Lu and Y. Yao, "Thread Voting DVFS for Manycore NoCs," IEEE Transactions on Computers, vol. 67, no. 10, pp. 1506-1524, 2018.
[46]
S. Wang et al., "WARD : Wear aware RAID design within SSDs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 11, pp. 2918-2928, 2018.
[47]
Z. Lu and X. Zhao, "xMAS-Based QoS Analysis Methodology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 2, pp. 364-377, 2018.
[48]
X. Zhao and Z. Lu, "A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink," ACM Transactions on Modeling and Computer Simulation, vol. 27, no. 3, 2017.
[49]
J. Wang et al., "ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs," IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 930-937, 2017.
[50]
Z. Lu and Y. Yao, "Dynamic Traffic Regulation in NoC-Based Systems," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 25, no. 2, pp. 556-569, 2017.
[51]
Q. Xiong et al., "Extending Real-Time Analysis for Wormhole NoCs," IEEE Transactions on Computers, vol. 66, no. 9, pp. 1532-1546, 2017.
[52]
Z. Lu and Y. Yao, "Marginal Performance : Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS," IEEE Transactions on Computers, vol. 66, no. 11, pp. 1903-1917, 2017.
[53]
M. Badawi, Z. Lu and A. Hemani, "Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture," Microprocessors and microsystems, vol. 54, pp. 47-59, 2017.
[54]
X. Chen et al., "Round-trip DRAM access fairness in 3D NoC-based many-core systems," ACM Transactions on Embedded Computing Systems, vol. 16, no. 5s, 2017.
[55]
J. Wang et al., "A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era," IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3406-3412, 2016.
[56]
J. Wang, Z. Lu and Y. Li, "A New CDMA Encoding/Decoding Method for on-Chip Communication Network," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 24, no. 4, pp. 1607-1611, 2016.
[57]
Z. Lu and Y. Yao, "Aggregate flow-based performance fairness in CMPs," ACM Transactions on Architecture and Code Optimization (TACO), vol. 13, no. 4, 2016.
[58]
F. Jafari, A. Jantsch and Z. Lu, "Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 24, no. 12, pp. 3387-3400, 2016.
[59]
X. Zhao and Z. Lu, "Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 6, pp. 986-999, 2015.
[60]
F. Jafari, Z. Lu and A. Jantsch, "Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels," ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 3, 2015.
[61]
S. Liu, J. Axel and Z. Lu, "MultiCS : Circuit switched NoC with multiple sub-networks and sub-channels," Journal of systems architecture, 2015.
[62]
[63]
S. Liu, A. Jantsch and Z. Lu, "A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 23, no. 10, pp. 2229-2233, 2014.
[64]
Y. Zhang et al., "A survey of memory architecture for 3D chip multi-processors," Microprocessors and microsystems, vol. 38, no. 5, pp. 415-430, 2014.
[65]
[66]
C. Feng et al., "Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 21, no. 6, pp. 1053-1066, 2013.
[67]
A. Eslami Kiasari, Z. Lu and A. Jantsch, "An Analytical Latency Model for Networks-on-Chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 21, no. 1, pp. 113-123, 2013.
[68]
Z. Zhang et al., "Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis," IEEE Transactions on Industrial Electronics, vol. 61, no. 4, pp. 2122-2135, 2013.
[69]
A. Eslami Kiasari, A. Jantsch and Z. Lu, "Mathematical formalisms for performance evaluation of networks-on-chip," ACM Computing Surveys, vol. 45, no. 3, pp. 38, 2013.
[71]
A. Naeem, A. Jantsch and Z. Lu, "Scalability Analysis of Memory Consistency Models in NoC-based Distributed Shared Memory SoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 5, pp. 760-773, 2013.
[72]
C. Feng et al., "A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip," IEICE transactions on information and systems, vol. E95D, no. 5, pp. 1519-1522, 2012.
[73]
Y. Chen et al., "A single-cycle output buffered router with layered switching for Networks-on-Chips," Computers & electrical engineering, vol. 38, no. 4, pp. 906-916, 2012.
[74]
M. Liu et al., "A survey of FPGA dynamic reconfiguration design methodology and applications," International Journal of Embedded and Real-Time Communication Systems, vol. 3, no. 2, pp. 23-39, 2012.
[75]
Z. Zhang et al., "Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things : concept and analysis," International Journal of Communication Systems, vol. 25, no. 9, pp. 1103-1121, 2012.
[76]
Z. Zhang et al., "Design and Optimization of a CDMA-based Multi-Reader Passive UHF RFID System for Dense Scenarios," IEICE transactions on communications, vol. E95B, no. 1, pp. 206-216, 2012.
[77]
W. Hu et al., "Multicast Path Setup Incorporating Evicting," Elektronika ir Elektrotechnika, no. 8, pp. 101-104, 2012.
[78]
H. She et al., "Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks," International Journal of Distributed Sensor Networks, pp. 232937, 2012.
[79]
W. Hu et al., "Self-selection pseudo-circuit : a clever crossbar pre- allocation," IEICE Electronics Express, vol. 9, no. 6, pp. 558-564, 2012.
[80]
C. Feng et al., "Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip," IEICE transactions on information and systems, vol. E95D, no. 4, pp. 1052-1061, 2012.
[81]
W. Hu et al., "TPSS : A flexible hardware support for unicast and multicast on networks-on-chip," Journal of Computers, vol. 7, no. 7, pp. 1743-1752, 2012.
[82]
M. Qiu et al., "Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors," Journal of systems architecture, vol. 58, no. 10, pp. 439-445, 2012.
[83]
C. -. Feng et al., "A 1-cycle 2 GHz bufferless router for network-on-chip," Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, vol. 33, no. 6, pp. 42-47, 2011.
[84]
M. Liu et al., "A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments," Computing in science & engineering (Print), vol. 13, no. 2, pp. 52-63, 2011.
[85]
X. Chen et al., "Cooperative communication based barrier synchronization in on-chip mesh architectures," IEICE Electronics Express, vol. 8, no. 22, pp. 1856-1862, 2011.
[86]
I. Anagnostopoulos et al., "Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations," IEEE Embedded Systems Letters, vol. 3, no. 2, pp. 66-69, 2011.
[87]
M. Liu et al., "FPGA-Based Particle Recognition in the HADES Experiment," IEEE Design & Test of Computers, vol. 28, no. 4, pp. 48-57, 2011.
[88]
X. Chen et al., "Hybrid distributed shared memory space in multi-core processors," Journal of Software, vol. 6, no. 12 SPEC. ISSUE, pp. 2369-2378, 2011.
[89]
N. Ma, Z. Lu and L. Zheng, "System design of full HD MVC decoding on mesh-based multicore NoCs," Microprocessors and microsystems, vol. 35, no. 2, pp. 217-229, 2011.
[90]
Y. Qian, Z. Lu and W. Dou, "Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 802-815, 2010.
[91]
F. Jafari et al., "Buffer Optimization in Network-on-Chip Through Flow Regulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1973-1986, 2010.
[92]
Y. Qian et al., "Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks," IEICE transactions on electronics, vol. E92C, no. 10, pp. 1276-1283, 2009.
[93]
Y. Qian, Z. Lu and W. Dou, "Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E92A, no. 12, pp. 3211-3220, 2009.
[94]
H. She et al., "Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks," International Journal of Software Engineering and Its Applications, vol. 2, no. 3, 2008.
[95]
Z. Lu et al., "Network-on Chip Micro-Benchmarks," Embedded Systems Design, no. September, 2008.
[96]
Z. Lu and A. Jantsch, "TDM virtual-circuit configuration for network-on-chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 16, no. 8, pp. 1021-1034, 2008.
[97]
Z. Lu and A. Jantsch, "Admitting and ejecting flits in wormhole-switched networks on chip," Iet Computers and Digital Techniques, vol. 1, no. 5, pp. 546-556, 2007.
[98]
I. Sander, A. Jantsch and Z. Lu, "Development and application of design transformations in ForSyDe," IEE Proceedings - Computers and digital Techniques, vol. 150, no. 5, pp. 313-320, 2003.

Conference papers

[99]
W. Zhu, Y. Chen and Z. Lu, "Activation in Network for NoC-Based Deep Neural Network Accelerator," in 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings, 2024.
[100]
Z. Lu and M. Liu, "Computational Network-on-Chip as Convolution Engine," in 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings, 2024.
[101]
X. Dong et al., "Gait Recognition Based on Modified OVR-CSP Fusion Feature and LSTM," in 2024 7th International Conference on Advanced Algorithms and Control Engineering, ICAACE 2024, 2024, pp. 1551-1554.
[102]
Z. Lu and A. Otto, "Health condition estimation for discrete power electronic devices under package failure," in 2024 IEEE International Conference on Prognostics and Health Management, ICPHM 2024, 2024, pp. 336-347.
[103]
Y. Chen et al., "Impact of Image Sensor Input Faults on Pruned Neural Networks for Object Detection," in 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024, 2024.
[104]
V. Geraeinejad et al., "MCLB : Dynamic Load Balancing and Implications on GPU Memory Controllers," in Proceedings - 2024 IEEE 37th International System-on-Chip Conference, SOCC 2024, 2024.
[105]
Z. Lu et al., "Age Feature Enhanced Neural Network for RUL Estimation of Power Electronic Devices," in 2023 IEEE International Conference on Prognostics and Health Management, ICPHM 2023, 2023, pp. 38-47.
[106]
P. Su, Z. Lu and D. Chen, "Combining Self-Organizing Map with Reinforcement Learning for Multivariate Time Series Anomaly Detection," in Proceedings 2023 IEEE International Conference on Systems, Man, and Cybernetics (SMC), 2023.
[107]
P. Su, Z. Lu and D. Chen, "Combining Self-Organizing Map with Reinforcement Learning for Multivariate Time Series Anomaly Detection," in 2023 IEEE International Conference on Systems, Man, and Cybernetics: Improving the Quality of Life, SMC 2023 - Proceedings, 2023, pp. 1964-1969.
[108]
Q. Liu et al., "ECG abnormality detection Based on Multi-domain combination features and LSTM," in 2023 4th International Conference on Computer Engineering and Application, ICCEA 2023, 2023, pp. 565-569.
[109]
Y. Wang et al., "FlexZNS : Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones," in Proceedings - 2023 IEEE 41st International Conference on Computer Design, ICCD 2023, 2023, pp. 291-299.
[110]
Z. Lu et al., "RUL Estimation for Power Electronic Devices Based on LESIT Equation," in 2023 PROGNOSTICS AND HEALTH MANAGEMENT CONFERENCE, PHM, 2023, pp. 47-54.
[111]
S. Shen et al., "A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography," in 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, pp. 1729-1733.
[112]
Y. Chen et al., "Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation," in Proceedings : 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022, 2022, pp. 239-246.
[113]
Q. Chen et al., "Enabling Energy-Efficient Inference for Self-Attention Mechanisms in Neural Networks," in 2022 Ieee International Conference On Artificial Intelligence Circuits And Systems (Aicas 2022) : Intelligent Technology In The Post-Pandemic Era, 2022, pp. 25-28.
[114]
I.-I. Sadou et al., "Inference Time Reduction of Deep Neural Networks on Embedded Devices : A Case Study," in 2022 25Th Euromicro Conference On Digital System Design (DSD), 2022, pp. 205-213.
[115]
Y. Hu et al., "LM-SVM-DT Based Working State Recognition for Washing Machine's Audio Signal," in 2022 IEEE International Conference on Artificial Intelligence and Computer Applications, ICAICA 2022, 2022, pp. 550-554.
[116]
Y. Chen et al., "Online Image Sensor Fault Detection for Autonomous Vehicles," in Proceedings : 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022, 2022, pp. 120-127.
[117]
Z. Lu et al., "Wearable pressure sensing for lower limb amputees," in BioCAS 2022 : IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Proceedings, 2022, pp. 105-109.
[118]
X. Hu and Z. Lu, "A Configurable Hardware Architecture for Runtime Application of Network Calculus," in Lecture Notes in Computer Science book series (LNTCS,volume 12639), 2021, pp. 203-216.
[119]
H. Chen et al., "A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation," in 2021 SCAS 2021/IEEE International Symposium on Circuits and Systems, 2021.
[120]
Q. Gao et al., "Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures," in 2021 Ieee International Symposium On Circuits And Systems (ISCAS), 2021.
[121]
W. Zhu and Z. Lu, "Evaluation of Time Series Clustering on Embedded Sensor Platform," in 2021 24TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2021), 2021, pp. 187-191.
[122]
W. Liu et al., "Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory," in PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, pp. 1729-1732.
[123]
E. Malekzadeh et al., "The Impact of Faults on DNNs : A Case Study," in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021.
[124]
H. Chen et al., "A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions," in IEEE International Symposium on Circuits and Systems, ISCAS 2020, 2020.
[125]
X. Hu and Z. Lu, "End-to-End System QoS Modeling based on Network Calculus : A Multi-Media Case Study," in ACM International Conference Proceeding Series, 2020, pp. 80-83.
[126]
B. Wang and Z. Lu, "Supporting QoS in AXI4 based Communication Architecture," in 2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, pp. 548-553.
[127]
B. Wang, Z. Lu and S. Chen, "ANN Based Admission Control for On-Chip Networks," in PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019.
[128]
B. Wang and Z. Lu, "Advance Virtual Channel Reservation," in 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, pp. 1178-1183.
[129]
M. Becker, Z. Lu and D. Chen, "An adaptive resource provisioning scheme for industrial SDN networks," in IEEE International Conference on Industrial Informatics (INDIN), 2019, pp. 877-880.
[130]
W. Liu et al., "Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash," in 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, pp. 312-315.
[131]
M. Törngren et al., "Competence Networks in the Era of CPS : Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center," in Proceedings of the International Workshop on Design, Modeling, and Evaluation of Cyber Physical Systems, CyPhy 2019 : Workshop on Embedded Systems and Cyber-Physical Systems Education, 2019, pp. 264-283.
[132]
Y. Fu et al., "Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs," in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019.
[133]
S. Chen and Z. Lu, "Hardware acceleration of multilayer perceptron based on inter-layer optimization," in Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, 2019, pp. 164-172.
[134]
G. Du et al., "NR-MPA : Non-recovery compression based multi-path packet-connected-circuit architecture of convolution neural networks accelerator," in Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, 2019, pp. 173-176.
[135]
Q. Chen et al., "Smilodon : An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning," in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019.
[136]
F. Wu et al., "Characterizing 3D Charge Trap NAND Flash : Observations, Analyses and Applications," in Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018, 2018, pp. 381-388.
[137]
H. Lv et al., "Exploiting Minipage-level Mapping to Improve Write Efficiency of NAND Flash," in 2018 IEEE INTERNATIONAL CONFERENCE ON NETWORKING, ARCHITECTURE AND STORAGE (NAS), 2018.
[138]
Y. Yao and Z. Lu, "INPG : Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores," in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, pp. 15-26.
[139]
Z. Lu et al., "Message from the Chairs," in 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018; Torino; Italy; 4 October 2018 through 5 October 2018, 2018.
[140]
X. Shi et al., "Program Error Rate-based Wear Leveling for NAND Hash Memory," in PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, pp. 1241-1246.
[141]
M. Becker, Z. Lu and D. Chen, "Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures," in Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2018, pp. 4096-4101.
[142]
D. Chen and Z. Lu, "A methodological framework for model-based self-management of services and components in dependable cyber-physical systems," in 12th International Conference on Dependability and Complex Systems, DepCoS-RELCOMEX 2017, 2017, pp. 97-105.
[143]
Y. Zhu et al., "ALARM : A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability," in 2017 IEEE International Conference on Networking, Architecture, and Storage, NAS 2017 - Proceedings, 2017.
[144]
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