Publications by Zhonghai Lu
Refereegranskade
Artiklar
[1]
W. Song et al., "Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data," IEEE Access, vol. 12, pp. 11850-11864, 2024.
[2]
L. Zhu et al., "A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow," IEEE design & test, vol. 40, no. 6, pp. 39-50, 2023.
[3]
Q. Liu et al., "Health warning based on 3R ECG Sample's combined features and LSTM," Computers in Biology and Medicine, vol. 162, 2023.
[4]
Y. Wang et al., "Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs," IEEE Transactions on Computers, vol. 72, no. 11, pp. 3127-3139, 2023.
[5]
[6]
Z. Lu et al., "Remaining useful lifetime estimation for discrete power electronic devices using physics-informed neural network," Scientific Reports, vol. 13, no. 1, 2023.
[7]
L. Cui et al., "A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 6, pp. 1971-1975, 2022.
[8]
Y. Zhang et al., "Base-2 Softmax Function : Suitability for Training and Efficient Hardware Implementation," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 69, no. 9, pp. 3605-3618, 2022.
[9]
B. Wang and Z. Lu, "Flexible and Efficient QoS Provisioning in AXI4-based Network-on-Chip Architecture," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1523-1536, 2022.
[10]
H. Chen et al., "Huicore : A Generalized Hardware Accelerator for Complicated Functions," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 69, no. 6, pp. 2463-2476, 2022.
[11]
W. Zhu et al., "Redundancy Reduction for Sensor Deployment in Prosthetic Socket : A Case Study," Sensors, vol. 22, no. 9, pp. 3103, 2022.
[12]
X. Hu and Z. Lu, "A Configurable Hardware Architecture for Runtime Application of Network Calculus," International journal of parallel programming, vol. 49, no. 5, pp. 745-760, 2021.
[13]
W. Liu et al., "DEPS : Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 66-77, 2021.
[14]
H. Chen et al., "Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 68, no. 8, pp. 3293-3304, 2021.
[15]
J. Wang et al., "Optimal Sprinting Pattern in Thermal Constrained CMPs," IEEE Transactions on Emerging Topics in Computing, 2021.
[16]
H. Chen et al., "Symmetric-Mapping LUT-Based Method and Architecture for Computing X-Y-Like Functions," IEEE Transactions on Circuits and Systems Part 1 : Regular Papers, vol. 68, no. 3, pp. 1231-1244, 2021.
[17]
Z. Qin et al., "A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 67, no. 12, pp. 3422-3426, 2020.
[18]
Z. Qin et al., "A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing," IEEE Access, vol. 8, pp. 46229-46241, 2020.
[19]
B. Wang and Z. Lu, "Advance Virtual Channel Reservation," IEEE Transactions on Computers, vol. 69, no. 9, pp. 1320-1334, 2020.
[20]
Q. Chen et al., "An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 28, no. 6, pp. 1540-1544, 2020.
[21]
H. Chen et al., "An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions," Electronics, vol. 9, no. 10, 2020.
[22]
R. Ma et al., "BlockHammer : Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2020.
[23]
B. Wang and Z. Lu, "Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture," IEEE Access, vol. 8, pp. 182663-182678, 2020.
[24]
H. Chen et al., "Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 67, no. 11, pp. 2652-2656, 2020.
[25]
Y. Yao and Z. Lu, "Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS," IEEE Transactions on Computers, vol. 69, no. 3, pp. 410-426, 2020.
[26]
S. Guo et al., "Securing IoT Space via Hardware Trojan Detection," IEEE Internet of Things Journal, vol. 7, no. 11, pp. 11115-11122, 2020.
[27]
Z. Qin et al., "Accelerating Deep Neural Networks by Combining Block-Circulant Matrices and Low-Precision Weights," Electronics, vol. 8, no. 1, 2019.
[28]
Q. Chen et al., "An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks," Electronics, vol. 8, no. 4, 2019.
[29]
W. Zhang, Q. Cao and Z. Lu, "Bit-Flipping Schemes Upon MLC Flash : Investigation, Implementation, and Evaluation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 4, pp. 780-784, 2019.
[30]
R. Ma et al., "RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory," IEEE Access, vol. 7, pp. 44696-44708, 2019.
[31]
Y. Zhou et al., "SCORE : A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory," ACM Transactions on Architecture and Code Optimization (TACO), vol. 15, no. 4, 2019.
[32]
G. Du et al., "SSS : Self-aware System-on-chip Using a Static-dynamic Hybrid Method," ACM Journal on Emerging Technologies in Computing Systems, vol. 15, no. 3, 2019.
[33]
S. Guo et al., "Security-Aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs," IEEE Transactions on Industrial Informatics, vol. 15, no. 10, pp. 5435-5443, 2019.
[34]
Z. Chen et al., "Toward FPGA Security in IoT : A New Detection Technique for Hardware Trojans," IEEE Internet of Things Journal, vol. 6, no. 4, pp. 7061-7068, 2019.
[35]
J. Wang et al., "A New Parallel CODEC Technique for CDMA NoCs," IEEE Transactions on Industrial Electronics, vol. 65, no. 8, pp. 6527-6537, 2018.
[36]
X. Chen et al., "A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 26, no. 10, pp. 1953-1966, 2018.
[37]
Y. -. Long, H. -. Shen and Z. Lu, "Analysis and Evaluation of Delay Bounds for Multiplexing Models Based on Network Calculus," Tien Tzu Hsueh Pao, vol. 46, no. 8, pp. 1815-1821, 2018.
[38]
Z. Wang et al., "Cache Access Fairness in 3D Mesh-Based NUCA," IEEE Access, vol. 6, pp. 42984-42996, 2018.
[39]
Q. Xiong et al., "Characterizing 3D Floating Gate NAND Flash : Observations, Analyses, and Implications," ACM Transactions on Storage, vol. 14, no. 2, 2018.
[40]
Y. Long, Z. Lu and H. Shen, "Composable Worst-Case Delay Bound Analysis Using Network Calculus," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3, pp. 705-709, 2018.
[41]
C. Li et al., "RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router," IEEE Transactions on Parallel and Distributed Systems, vol. 29, no. 9, pp. 2090-2104, 2018.
[42]
Z. Lu and Y. Yao, "Thread Voting DVFS for Manycore NoCs," IEEE Transactions on Computers, vol. 67, no. 10, pp. 1506-1524, 2018.
[43]
S. Wang et al., "WARD : Wear aware RAID design within SSDs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 11, pp. 2918-2928, 2018.
[44]
Z. Lu and X. Zhao, "xMAS-Based QoS Analysis Methodology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 2, pp. 364-377, 2018.
[45]
X. Zhao and Z. Lu, "A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink," ACM Transactions on Modeling and Computer Simulation, vol. 27, no. 3, 2017.
[46]
J. Wang et al., "ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs," IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 930-937, 2017.
[47]
Z. Lu and Y. Yao, "Dynamic Traffic Regulation in NoC-Based Systems," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 25, no. 2, pp. 556-569, 2017.
[48]
Q. Xiong et al., "Extending Real-Time Analysis for Wormhole NoCs," IEEE Transactions on Computers, vol. 66, no. 9, pp. 1532-1546, 2017.
[49]
Z. Lu and Y. Yao, "Marginal Performance : Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS," IEEE Transactions on Computers, vol. 66, no. 11, pp. 1903-1917, 2017.
[50]
M. Badawi, Z. Lu and A. Hemani, "Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture," Microprocessors and microsystems, vol. 54, pp. 47-59, 2017.
[51]
X. Chen et al., "Round-trip DRAM access fairness in 3D NoC-based many-core systems," ACM Transactions on Embedded Computing Systems, vol. 16, no. 5s, 2017.
[52]
J. Wang et al., "A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era," IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3406-3412, 2016.
[53]
J. Wang, Z. Lu and Y. Li, "A New CDMA Encoding/Decoding Method for on-Chip Communication Network," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 24, no. 4, pp. 1607-1611, 2016.
[54]
Z. Lu and Y. Yao, "Aggregate flow-based performance fairness in CMPs," ACM Transactions on Architecture and Code Optimization (TACO), vol. 13, no. 4, 2016.
[55]
F. Jafari, A. Jantsch and Z. Lu, "Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 24, no. 12, pp. 3387-3400, 2016.
[56]
X. Zhao and Z. Lu, "Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 6, pp. 986-999, 2015.
[57]
F. Jafari, Z. Lu and A. Jantsch, "Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels," ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 3, 2015.
[58]
S. Liu, J. Axel and Z. Lu, "MultiCS : Circuit switched NoC with multiple sub-networks and sub-channels," Journal of systems architecture, 2015.
[59]
X. Chen et al., "Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications," Journal of Electrical and Computer Engineering, vol. 2015, 2015.
[60]
S. Liu, A. Jantsch and Z. Lu, "A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 23, no. 10, pp. 2229-2233, 2014.
[61]
Y. Zhang et al., "A survey of memory architecture for 3D chip multi-processors," Microprocessors and microsystems, vol. 38, no. 5, pp. 415-430, 2014.
[62]
X. Chen et al., "Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs," IEICE Electronics Express, vol. 11, no. 18, pp. 20140542, 2014.
[63]
C. Feng et al., "Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 21, no. 6, pp. 1053-1066, 2013.
[64]
A. Eslami Kiasari, Z. Lu and A. Jantsch, "An Analytical Latency Model for Networks-on-Chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 21, no. 1, pp. 113-123, 2013.
[65]
Z. Zhang et al., "Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis," IEEE Transactions on Industrial Electronics, vol. 61, no. 4, pp. 2122-2135, 2013.
[66]
A. Eslami Kiasari, A. Jantsch and Z. Lu, "Mathematical formalisms for performance evaluation of networks-on-chip," ACM Computing Surveys, vol. 45, no. 3, pp. 38, 2013.
[67]
X. Chen et al., "Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property," Computers & electrical engineering, vol. 39, no. 2, pp. 596-612, 2013.
[68]
A. Naeem, A. Jantsch and Z. Lu, "Scalability Analysis of Memory Consistency Models in NoC-based Distributed Shared Memory SoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 5, pp. 760-773, 2013.
[69]
C. Feng et al., "A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip," IEICE transactions on information and systems, vol. E95D, no. 5, pp. 1519-1522, 2012.
[70]
Y. Chen et al., "A single-cycle output buffered router with layered switching for Networks-on-Chips," Computers & electrical engineering, vol. 38, no. 4, pp. 906-916, 2012.
[71]
M. Liu et al., "A survey of FPGA dynamic reconfiguration design methodology and applications," International Journal of Embedded and Real-Time Communication Systems, vol. 3, no. 2, pp. 23-39, 2012.
[72]
Z. Zhang et al., "Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things : concept and analysis," International Journal of Communication Systems, vol. 25, no. 9, pp. 1103-1121, 2012.
[73]
Z. Zhang et al., "Design and Optimization of a CDMA-based Multi-Reader Passive UHF RFID System for Dense Scenarios," IEICE transactions on communications, vol. E95B, no. 1, pp. 206-216, 2012.
[74]
W. Hu et al., "Multicast Path Setup Incorporating Evicting," Elektronika ir Elektrotechnika, no. 8, pp. 101-104, 2012.
[75]
H. She et al., "Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks," International Journal of Distributed Sensor Networks, pp. 232937, 2012.
[76]
W. Hu et al., "Self-selection pseudo-circuit : a clever crossbar pre- allocation," IEICE Electronics Express, vol. 9, no. 6, pp. 558-564, 2012.
[77]
C. Feng et al., "Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip," IEICE transactions on information and systems, vol. E95D, no. 4, pp. 1052-1061, 2012.
[78]
W. Hu et al., "TPSS : A flexible hardware support for unicast and multicast on networks-on-chip," Journal of Computers, vol. 7, no. 7, pp. 1743-1752, 2012.
[79]
M. Qiu et al., "Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors," Journal of systems architecture, vol. 58, no. 10, pp. 439-445, 2012.
[80]
C. -. Feng et al., "A 1-cycle 2 GHz bufferless router for network-on-chip," Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, vol. 33, no. 6, pp. 42-47, 2011.
[81]
M. Liu et al., "A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments," Computing in science & engineering (Print), vol. 13, no. 2, pp. 52-63, 2011.
[82]
X. Chen et al., "Cooperative communication based barrier synchronization in on-chip mesh architectures," IEICE Electronics Express, vol. 8, no. 22, pp. 1856-1862, 2011.
[83]
I. Anagnostopoulos et al., "Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations," IEEE Embedded Systems Letters, vol. 3, no. 2, pp. 66-69, 2011.
[84]
M. Liu et al., "FPGA-Based Particle Recognition in the HADES Experiment," IEEE Design & Test of Computers, vol. 28, no. 4, pp. 48-57, 2011.
[85]
X. Chen et al., "Hybrid distributed shared memory space in multi-core processors," Journal of Software, vol. 6, no. 12 SPEC. ISSUE, pp. 2369-2378, 2011.
[86]
N. Ma, Z. Lu and L. Zheng, "System design of full HD MVC decoding on mesh-based multicore NoCs," Microprocessors and microsystems, vol. 35, no. 2, pp. 217-229, 2011.
[87]
Y. Qian, Z. Lu and W. Dou, "Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 802-815, 2010.
[88]
F. Jafari et al., "Buffer Optimization in Network-on-Chip Through Flow Regulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1973-1986, 2010.
[89]
Y. Qian et al., "Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks," IEICE transactions on electronics, vol. E92C, no. 10, pp. 1276-1283, 2009.
[90]
Y. Qian, Z. Lu and W. Dou, "Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E92A, no. 12, pp. 3211-3220, 2009.
[91]
H. She et al., "Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks," International Journal of Software Engineering and Its Applications, vol. 2, no. 3, 2008.
[92]
[93]
Z. Lu and A. Jantsch, "TDM virtual-circuit configuration for network-on-chip," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 16, no. 8, pp. 1021-1034, 2008.
[94]
Z. Lu and A. Jantsch, "Admitting and ejecting flits in wormhole-switched networks on chip," Iet Computers and Digital Techniques, vol. 1, no. 5, pp. 546-556, 2007.
[95]
I. Sander, A. Jantsch and Z. Lu, "Development and application of design transformations in ForSyDe," IEE Proceedings - Computers and digital Techniques, vol. 150, no. 5, pp. 313-320, 2003.
Konferensbidrag
[96]
Z. Lu et al., "Age Feature Enhanced Neural Network for RUL Estimation of Power Electronic Devices," in 2023 IEEE International Conference on Prognostics and Health Management, ICPHM 2023, 2023, pp. 38-47.
[97]
P. Su, Z. Lu and D. Chen, "Combining Self-Organizing Map with Reinforcement Learning for Multivariate Time Series Anomaly Detection," in Proceedings 2023 IEEE International Conference on Systems, Man, and Cybernetics (SMC), 2023.
[98]
L. Liu, Z. Lu and D. Chen, "Combining Self-Organizing Map with Reinforcement Learning for Multivariate Time Series Anomaly Detection," in 2023 IEEE International Conference on Systems, Man, and Cybernetics: Improving the Quality of Life, SMC 2023 - Proceedings, 2023, pp. 1964-1969.
[99]
Q. Liu et al., "ECG abnormality detection Based on Multi-domain combination features and LSTM," in 2023 4th International Conference on Computer Engineering and Application, ICCEA 2023, 2023, pp. 565-569.
[100]
Y. Wang et al., "FlexZNS : Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones," in Proceedings - 2023 IEEE 41st International Conference on Computer Design, ICCD 2023, 2023, pp. 291-299.
[101]
Z. Lu et al., "RUL Estimation for Power Electronic Devices Based on LESIT Equation," in 2023 PROGNOSTICS AND HEALTH MANAGEMENT CONFERENCE, PHM, 2023, pp. 47-54.
[102]
S. Shen et al., "A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography," in 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, pp. 1729-1733.
[103]
Y. Chen et al., "Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation," in Proceedings : 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022, 2022, pp. 239-246.
[104]
Q. Chen et al., "Enabling Energy-Efficient Inference for Self-Attention Mechanisms in Neural Networks," in 2022 Ieee International Conference On Artificial Intelligence Circuits And Systems (Aicas 2022) : Intelligent Technology In The Post-Pandemic Era, 2022, pp. 25-28.
[105]
I.-I. Sadou et al., "Inference Time Reduction of Deep Neural Networks on Embedded Devices : A Case Study," in 2022 25Th Euromicro Conference On Digital System Design (DSD), 2022, pp. 205-213.
[106]
Y. Hu et al., "LM-SVM-DT Based Working State Recognition for Washing Machine's Audio Signal," in 2022 IEEE International Conference on Artificial Intelligence and Computer Applications, ICAICA 2022, 2022, pp. 550-554.
[107]
Y. Chen et al., "Online Image Sensor Fault Detection for Autonomous Vehicles," in Proceedings : 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022, 2022, pp. 120-127.
[108]
Z. Lu et al., "Wearable pressure sensing for lower limb amputees," in BioCAS 2022 : IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Proceedings, 2022, pp. 105-109.
[109]
X. Hu and Z. Lu, "A Configurable Hardware Architecture for Runtime Application of Network Calculus," in Lecture Notes in Computer Science book series (LNTCS,volume 12639), 2021, pp. 203-216.
[110]
H. Chen et al., "A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation," in 2021 SCAS 2021/IEEE International Symposium on Circuits and Systems, 2021.
[111]
Q. Gao et al., "Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures," in 2021 Ieee International Symposium On Circuits And Systems (ISCAS), 2021.
[112]
W. Zhu and Z. Lu, "Evaluation of Time Series Clustering on Embedded Sensor Platform," in 2021 24TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2021), 2021, pp. 187-191.
[113]
W. Liu et al., "Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory," in PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, pp. 1729-1732.
[114]
E. Malekzadeh et al., "The Impact of Faults on DNNs : A Case Study," in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021.
[115]
H. Chen et al., "A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions," in IEEE International Symposium on Circuits and Systems, ISCAS 2020, 2020.
[116]
X. Hu and Z. Lu, "End-to-End System QoS Modeling based on Network Calculus : A Multi-Media Case Study," in ACM International Conference Proceeding Series, 2020, pp. 80-83.
[117]
B. Wang and Z. Lu, "Supporting QoS in AXI4 based Communication Architecture," in 2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, pp. 548-553.
[118]
B. Wang, Z. Lu and S. Chen, "ANN Based Admission Control for On-Chip Networks," in PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019.
[119]
B. Wang and Z. Lu, "Advance Virtual Channel Reservation," in 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, pp. 1178-1183.
[120]
M. Becker, Z. Lu and D. Chen, "An adaptive resource provisioning scheme for industrial SDN networks," in IEEE International Conference on Industrial Informatics (INDIN), 2019, pp. 877-880.
[121]
W. Liu et al., "Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash," in 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, pp. 312-315.
[122]
M. Törngren et al., "Competence Networks in the Era of CPS : Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center," in Proceedings of the International Workshop on Design, Modeling, and Evaluation of Cyber Physical Systems, CyPhy 2019 : Workshop on Embedded Systems and Cyber-Physical Systems Education, 2019, pp. 264-283.
[123]
Y. Fu et al., "Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs," in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019.
[124]
S. Chen and Z. Lu, "Hardware acceleration of multilayer perceptron based on inter-layer optimization," in Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, 2019, pp. 164-172.
[125]
G. Du et al., "NR-MPA : Non-recovery compression based multi-path packet-connected-circuit architecture of convolution neural networks accelerator," in Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, 2019, pp. 173-176.
[126]
Q. Chen et al., "Smilodon : An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning," in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019.
[127]
F. Wu et al., "Characterizing 3D Charge Trap NAND Flash : Observations, Analyses and Applications," in Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018, 2018, pp. 381-388.
[128]
H. Lv et al., "Exploiting Minipage-level Mapping to Improve Write Efficiency of NAND Flash," in 2018 IEEE INTERNATIONAL CONFERENCE ON NETWORKING, ARCHITECTURE AND STORAGE (NAS), 2018.
[129]
Y. Yao and Z. Lu, "INPG : Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores," in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, pp. 15-26.
[130]
Z. Lu et al., "Message from the Chairs," in 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018; Torino; Italy; 4 October 2018 through 5 October 2018, 2018.
[131]
X. Shi et al., "Program Error Rate-based Wear Leveling for NAND Hash Memory," in PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, pp. 1241-1246.
[132]
M. Becker, Z. Lu and D. Chen, "Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures," in Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2018, pp. 4096-4101.
[133]
D. Chen and Z. Lu, "A methodological framework for model-based self-management of services and components in dependable cyber-physical systems," in 12th International Conference on Dependability and Complex Systems, DepCoS-RELCOMEX 2017, 2017, pp. 97-105.
[134]
Y. Zhu et al., "ALARM : A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability," in 2017 IEEE International Conference on Networking, Architecture, and Storage, NAS 2017 - Proceedings, 2017.
[135]
Q. Xiong et al., "Characterizing 3D floating gate NAND flash," in SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2017, pp. 31-32.
[136]
D. Chen and Z. Lu, "IMBSA 2017: Model-Based Safety and Assessment," in Model-Based Safety and Assessment - 5th International Symposium, Trento, Italy, September 11–13, 2017, 2017, pp. 227-240.
[137]
S. Wang et al., "Lifetime adaptive ECC in NAND flash page management," in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, pp. 1253-1256.
[138]
Y. Yao and Z. Lu, "Work-in-progress : Prediction based convolution neural network acceleration," in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017, 2017.
[139]
G. Du et al., "Work-in-progress : SSS: Self-aware system-on-chip using static-dynamic hybrid method," in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017, 2017.
[140]
N. Ma et al., "A 101.4 GOPS/W Reconfigurable and Scalable Control-centric Embedded Processor for Domain-specific Applications," in Proceedings - IEEE International Symposium on Circuits and Systems, 2016, pp. 1746-1749.
[141]
Z. Lu, "Automotive Ethernet : Towards TSN and Beyond," in COMPUTER SAFETY, RELIABILITY, AND SECURITY, SAFECOMP 2016, 2016.
[142]
Y. Yao and Z. Lu, "DVFS for NoCs in CMPs : A thread voting approach," in 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016, pp. 309-320.
[143]
M. Badawi, Z. Lu and A. Hemani, "Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture," in 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, pp. 575-583.
[144]
Y. Yao and Z. Lu, "Memory-Access Aware DVFS for Network-on-Chip in CMPs," in PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, pp. 1433-1436.
[145]
X. Chen et al., "Multi-bit Transient Fault Control for NoC Links Using 2D Fault Coding Method," in 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2016.
[146]
G. Du et al., "OLITS : An Ohm's Law-like Traffic Splitting Model Based on Congestion Prediction," in PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, pp. 1000-1005.
[147]
Y. Yao and Z. Lu, "Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs," in Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016, 2016, pp. 279-290.
[148]
Q. Xiong et al., "Real-time analysis for wormhole NoC : Revisited and revised," in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2016, pp. 75-80.
[149]
M. Badawi, Z. Lu and A. Hemani, "Service-Guaranteed Multi-Port PacketMemory for Parallel Protocol Processing Architecture," in Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, 2016, pp. 408-412.
[150]
X. Chen et al., "Achieving memory access equalization via round-trip routing latency prediction in 3D many-core NoCs," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2015, pp. 398-403.
[151]
X. Zhao and Z. Lu, "Backlog bound analysis for virtual-channel routers," in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 422-427.
[152]
Y. Zhang et al., "Exploring stacked main memory architecture for 3D GPGPUs," in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, 2015.
[153]
S. Liu, Z. Lu and A. Jantsch, "Highway in TDM NoCs," in Proceedings of the Ninth ACM/IEEE International Symposium on Networks-on-Chip (NoCS'15), 2015.
[154]
N. Ma et al., "Implementing MVC Decoding on Homogeneous NoCs : Circuit Switching or Wormhole Switching," in 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2015, pp. 387-391.
[155]
C. Feng et al., "Performance analysis of on-chip bufferless router with multi-ejection ports," in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, 2015.
[156]
Z. Lu, Y. Yao and Y. Jiang, "Towards stochastic delay bound analysis for network-on-chip," in Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, 2015, pp. 64-71.
[157]
A. Saggio et al., "Validating delay bounds in networks on chip : Tightness and pitfalls," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2015, pp. 404-409.
[158]
N. Ma et al., "A Hierarchical Reconfigurable Micro-coded Multi-core Processor for IoT Applications," in 2014 9TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), 2014.
[159]
G. Du et al., "An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs," in Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, 2014, pp. 49-56.
[160]
Y. Long, Z. Lu and X. Yan, "Analysis and evaluation of per-flow delay bound for multiplexing models," in Proceedings -Design, Automation and Test in Europe, DATE, 2014.
[161]
M. Badawi, A. Hemani and Z. Lu, "Customizable Coarse-grained Energy-efficient Reconfigurable Packet Processing Architecture," in Proceedings Of The 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2014, pp. 30-35.
[162]
X. Zhao and Z. Lu, "Empowering study of delay bound tightness with simulated annealing," in Proceedings -Design, Automation and Test in Europe, DATE, 2014.
[163]
Y. Yao and Z. Lu, "Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems," in 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp. 343-348.
[164]
S. Liu, A. Jantsch and Z. Lu, "Parallel probe based dynamic connection setup in TDM NoCs," in 17th Design, Automation and Test in Europe, DATE 2014, 24 - 28 March 2014, Dresden, 2014.
[165]
Y. Zhang et al., "Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips," in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, pp. 1961-1964.
[166]
S. Liu, A. Jantsch and Z. Lu, "Analysis and evaluation of circuit switched NoC and packet switched NoC," in Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, 2013, pp. 21-28.
[167]
X. Zhao and Z. Lu, "Per-flow delay bound analysis based on a formalized microarchitectural model," in 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013, 2013, p. 6558411.
[168]
X. Jiang et al., "An enhanced iot gateway in a broadcast system," in Proceedings - IEEE 9th International Conference on Ubiquitous Intelligence and Computing and IEEE 9th International Conference on Autonomic and Trusted Computing, UIC-ATC 2012, 2012, pp. 746-751.
[169]
A. Eslami Kiasari et al., "Analytical approaches for performance evaluation of networks-on-chip," in CASES'12 - Proceedings of the 2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Co-located with ESWEEK, 2012, pp. 211-212.
[170]
A. Naeem, A. Jantsch and Z. Lu, "Architecture Support and Comparison of Three Memory Consistency Models in NoC based Syst," in Proceedings of 15th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD 2012), 2012, pp. 304-311.
[171]
Z. Lu and Y. Wang, "Dynamic flow regulation for IP integration on network-on-chip," in Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, 2012, pp. 115-123.
[172]
X. Jiang et al., "Lessons of IOT effects on backbone networks learnt from traffic characteristics," in Int. Conf. Wirel. Commun., Networking Mob. Comput., WiCOM, 2012.
[173]
P. Schamberger et al., "Modeling and power evaluation of on-chip router components in spintronics," in Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, 2012, pp. 51-58.
[174]
S. Liu, A. Jantsch and Z. Lu, "Parallel Probing : Dynamic and constant time setup procedure in circuit switching NoC," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 2012, pp. 1289-1294.
[175]
A. Naeem, A. Jantsch and Z. Lu, "Scalability analysis of release and sequential consistency models in NoC based multicore systems," in 2012 International Symposium on System on Chip, SoC 2012, 2012, p. 6376350.
[176]
H. She, Z. Lu and A. Jantsch, "System-level evaluation of sensor networks deployment strategies : Coverage, lifetime and cost," in 2012 8th International Wireless Communications And Mobile Computing Conference (IWCMC), 2012, pp. 549-554.
[177]
F. Jafari, A. Jantsch and Z. Lu, "Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling," in Proceedings of the Design and Test in Europe Conference (DATE), 2012, pp. 538-541.
[178]
G. Du et al., "Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing," in CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK, 2012, pp. 123-132.
[179]
C. Feng et al., "A Low-overhead Fault-aware Deflection Routing Algorithm for 3D Network-on-Chip," in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 2011, pp. 19-24.
[180]
Y. Chen et al., "A deadlock-free fault-tolerant routing algorithm based on pseudo-receiving mechanism for networks-on-chip of CMP," in 2011 International Conference on Multimedia Technology, ICMT 2011, 2011, pp. 2825-2828.
[181]
W. Hu et al., "A flexible configuration approach for fault-tolerant multicast/unicast," in IEEE Int. Conf. Commun. Softw. Networks, ICCSN, 2011, pp. 393-396.
[182]
Z. Lu, "Cross Clock-Domain TDM Virtual Circuits for Networks on Chips," in NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, 2011, pp. 209-216.
[183]
C. Feng et al., "Evaluation of Deflection Routing on Various NoC Topologies," in Proceedings of the IEEE International Conference on ASIC (ASICON), 2011.
[184]
M. Liu et al., "FPGA-based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments," in Reconfigurable Computing : Architectures, Tools And Applications, 2011, pp. 169-180.
[185]
H. Su et al., "Jamming-Resilient Multi-Radio Multi-Channel Multihop Wireless Network for Smart Grid," in In Proceedings of the 7th ACM Annual Cyber Security and Information Intelligence Research Workshop (CSIIR’11), 2011.
[186]
H. She et al., "Modeling and Analysis of Rayleigh Fading Channels using Stochastic Network Calculus," in IEEE WCNC, 28-31 March 2011, 2011.
[187]
W. Hu et al., "Network-on-Chip Multicasting with Low Latency Path Setup," in Proceedings of the VLSI-SoC Conference, 2011.
[188]
F. Jafari, A. Jantsch and Z. Lu, "Output Process of Variable Bit-Rate Flows in On-Chip Networks Based on Aggregate Scheduling," in Proceedings of the International Conference on Computer Design, 2011, pp. 445-446.
[189]
W. Hu et al., "Power-efficient Tree-based Multicast Support for Networks-on-Chip," in Proceedings of the Asian Pacific Design Automation Conference (ASPDAC), 2011, pp. 363-368.
[190]
A. Naeem et al., "Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems," in Proceedings of 16th ACM/IEEE Asia and South Pacific Design Automation Conference(ASP-DAC) 2011, 2011, pp. 154-159.
[191]
A. Naeem et al., "Realization and Scalability of Release and Protected Release Consistency Models in NoC based Systems," in Proceeding of 14th Euromicro Conference on Digital System Design, 2011, 2011, pp. 47-54.
[192]
Y. Chen et al., "Slice router : For fine-granularity fault-tolerant Networks-on-Chip," in 2011 International Conference on Multimedia Technology, ICMT 2011, 2011, pp. 3230-3233.
[193]
H. She et al., "Stochastic Coverage in Event-Driven Sensor Networks," in 2011 IEEE 22nd International Symposium On Personal Indoor And Mobile Radio Communications (PIMRC), 2011, pp. 915-919.
[194]
B. Candaele et al., "The MOSART Mapping Optimization for multi-core Architectures," in VLSI 2010 Annual Symposium, 2011, pp. 181-195.
[195]
A. Eslami Kiasari, A. Jantsch and Z. Lu, "A Framework for Designing Congestion-Aware Deterministic Routing," in NoCArc '10 Proceedings of the Third International Workshop on Network on Chip Architectures, 2010, pp. 45-50.
[196]
C. Feng et al., "A Reconfigurable Fault-tolerant Deflection Routing Algorithm Based on Reinforcement Learning for Networks-on-Chip," in Proceedings of the International Workshop on Network on Chip Architectures (NoCArc), 2010.
[197]
Y. Chen et al., "A Trace-driven Hardware-level Simulator for Design and Verification of Network-on-Chips," in 2011 INTERNATIONAL CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND AUTOMATION (CCCA 2011), VOL II, 2010, pp. 32-35.
[198]
Z. Zhang et al., "A low delay multiple reader passive RFID system using orthogonal TH-PPM IR-UWB," in Proceedings - International Conference on Computer Communications and Networks, ICCCN, 2010.
[199]
X. Chen et al., "Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips," in 3rd IEEE International Conference on Computer and Electrical Engineering (ICCEE), 2010.
[200]
Z. Zhang et al., "COSMO : CO-simulation with MATLAB and OMNeT++ for indoor wireless networks," in 2010 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE GLOBECOM 2010, 2010.
[201]
M. Liu et al., "FPGA-based adaptive computing for correlated multi-stream processing," in Proceedings -Design, Automation and Test in Europe, DATE, 2010, pp. 973-976.
[202]
C. Feng et al., "FoN : Fault-on-Neighbor aware Routing Algorithm for Networks-on-Chip," in Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, pp. 441-446.
[203]
X. Chen et al., "Handling Shared Variable Synchronization in Multi-core Network-on-Chips with Distributed Memory," in Proceedings : IEEE International SOC Conference, SOCC 2010, 2010, pp. 467-472.
[204]
M. Liu et al., "Inter-process communication using pipes in FPGA-based adaptive computing," in Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, pp. 80-85.
[205]
B. Candaele et al., "Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach," in Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, pp. 518-523.
[206]
Z. Lu et al., "Message from the chairs," in 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43, 2010.
[207]
X. Chen et al., "Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism," in Proceedings of the IEEE Norchip Conference, 2010.
[208]
F. Jafari et al., "Optimal Regulation of Traffic Flows in Networks-on-Chip," in Proceedings of the Design Automation and Test Europe Conference (DATE), 2010, pp. 1621-1624.
[209]
Y. Qian, Z. Lu and Q. Dou, "QoS Scheduling for NoCs : Strict Priority Queueing versus Weighted Round Robin," in 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, pp. 52-59.
[210]
M. Liu et al., "Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations," in Proceedings of the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip, 2010, pp. 149-152.
[211]
X. Chen et al., "Run-time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips," in The 3rd IEEE International Symposium on Parallel Architectures, Algorithms and Programming (PAAP 2010), 2010, pp. 39-46.
[212]
A. Naeem et al., "Scalability of Weak Consistency in NoC based Multicore Architectures," in IEEE INT SYMP CIRC SYST PROC, 2010, pp. 3497-3500.
[213]
X. Chen et al., "Supporting Distributed Shared Memory on Multi-core Network-on-Chips Using a Dual Microcoded Controller," in Proceedings of the conference for Design Automation and Test in Europe, 2010, pp. 39-44.
[214]
X. Chen et al., "Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique," in Proceedings of the IEEE Annual Symposium on VLSI, 2010, pp. 462-463.
[215]
A. Y. Weldezion et al., "3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture," in 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, pp. 42-48.
[216]
Z. Lu, D. Brachos and A. Jantsch, "A Flow Regulator for On-Chip Communication," in IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2009, pp. 151-154.
[217]
M. Liu et al., "A Reconfigurable Design Framework for FPGA Adaptive Computing," in 2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS, 2009, pp. 439-444.
[218]
Y. Qian, Z. Lu and W. Dou, "Analysis of Communication Delay Bounds for Network on Chips," in PROCEEDINGS OF THE ASP-DAC 2009 : ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, pp. 7-12.
[219]
Y. Qian, Z. Lu and W. Dou, "Analysis of Worst-case Delay Bounds for Best-effort Communication in Wormhole Networks on Chip," in 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2009, pp. 44-53.
[220]
H. She et al., "Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks," in 2009 IEEE VEHICULAR TECHNOLOGY CONFERENCE, 2009, pp. 38-42.
[221]
Y. Qian, Z. Lu and W. Dou, "Applying Network Calculus for Performance Analysis of Self-Similar Traffic in On-Chip Networks," in IEEE/ACM/IFIP 2009 International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS’09), 2009, pp. 453-460.
[222]
Y. Qian, Z. Lu and W. Dou, "Applying Network Calculus for Worst-case Delay Bound Analysis in On-chip Networks," in Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009, pp. 113-118.
[223]
Y. Qian, Z. Lu and W. Dou, "Comparative Analysis of Worst-Case Communication Delay Bounds for 2D and 3D NoCs," in Proceedings of Workshop on 3D Integration and Interconnect-Centric Architectures held in conjunction with 15th International Symposium on High-Performance Computer Architecture, 2009.
[224]
L. Tong, Z. Lu and H. Zhang, "Exploration of slot allocation for on-chip TDM virtual circuits," in Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, pp. 127-132.
[225]
Z. Lu et al., "Flow Regulation for On-Chip Communication," in DATE : 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, pp. 578-581.
[226]
Y. Qian, Z. Lu and W. Dou, "From 2D to 3D NoCs : A Case Study of the worst-case Communication Performance," in IEEE/ACM 2009 International Conference on Computer-Aided Design (ICCAD’09), 2009, pp. 555-562.
[227]
M. Grange et al., "Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh," in 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, pp. 345-351.
[228]
M. Liu et al., "Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration," in FPL 09 : 19th International Conference on Field Programmable Logic and Applications, 2009, pp. 498-502.
[229]
A. Y. Weldezion et al., "Scalability of Network-on-Chip Communication Architecture for 3-D Meshes," in 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2009, pp. 114-123.
[230]
X. Chen et al., "Speedup Analysis of Data-parallel Applications on Multi-core NoCs," in Proceedings of the IEEE International Conference on ASIC (ASICON), 2009, pp. 105-108.
[231]
Y. Zhang et al., "Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip," in DTIS : 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, pp. 119-122.
[232]
Z. Lu and A. Jantsch, "Trends of Terascale Computing Chips in the Next Ten Years," in 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, pp. 62-66.
[233]
M. Liu et al., "Trigger algorithm development on FPGA-based Compute Nodes," in 2009 16th IEEE-NPSS Real Time Conference, 2009, pp. 478-484.
[234]
M. Liu et al., "ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments," in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, pp. 287-292.
[235]
Z. Lu, L. Xia and A. Jantsch, "Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip," in 2008 IEEE Workshop On Design And Diagnostics Of Electronic Circuits And Systems, Proceedings, 2008, pp. 92-97.
[236]
H. She et al., "Deterministic Worst-case Performance Analysis for Wireless Sensor Networks," in Proceedings of the International Wireless Communications and Mobile Computing Conference, 2008, pp. 1081-1086.
[237]
Y. Wang et al., "Dynamic TDM Virtual Circuit Implementation for NoCs," in Proceedings of Asia-Pacific Conference on Circuits and Systems (APCCAS’08), 2008, pp. 1533-1536.
[238]
A. W. Yin et al., "Monitoring Agent Based Autonomous Reconfigurable Network-on-Chip," in In DAC08 Workshop Digest in Diagnostic Services in Network-on-Chips, 2008.
[239]
M. Liu et al., "System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments," in 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, pp. 599-605.
[240]
H. She et al., "A Network-based System Architecture for Remote Medical Applications," in Proceedings of the Asia-Pacific Advanced Network Meeting, 2007.
[241]
M. Liu et al., "Hardware/Software co-design of a general-purpose computation platform in particle physics," in ICFPT 2007 : International Conference On Field-Programmable Technology, Proceedings, 2007, pp. 177-183.
[242]
Z. Lu, M. Liu and A. Jantsch, "Layered switching for networks on chip," in 2007 44th ACM/IEEE Design Automation Conference, Vols 1 And 2, 2007, pp. 122-127.
[243]
Z. Lu and A. Jantsch, "Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip," in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2007, pp. 18-25.
[244]
H. She et al., "Traffic splitting with network calculus for mesh sensor networks," in Proceedings of Future Generation Communication and Networking, FGCN 2007, 2007, pp. 371-376.
[245]
Z. Lu et al., "Using synchronizers for refining synchronous communication onto Hardware/Software architectures," in RSP 2007 : 18th IEEE/IFIP International Workshop on Rapid System Prototyping, Proceedings, 2007, pp. 143-149.
[246]
Z. Lu, B. Yin and A. Jantsch, "Connection-oriented multicasting in wormhole-switched networks on chip," in IEEE Computer Society Annual Symposium on VLSI, Proceedings - EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, pp. 205-210.
[247]
Z. Lu, M. Zhong and A. Jantsch, "Connection-oriented multicasting in wormhole-switched networks on chip," in Proceedings of the 16th ACM Great Lakes symposium on VLSI, 2006, pp. 296-301.
[248]
Z. Lu, I. Sander and A. Jantsch, "Refining synchronous communication onto network-on-chip best-effort services," in Applications of Specification and Design Languages for SoCs, 2006, pp. 23-38.
[249]
Z. Lu, I. Sander and A. Jantsch, "Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication," in DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, pp. 37-44.
[250]
Z. Lu et al., "A power efficient flit-admission scheme for wormhole-switched networks on chip," in WMSCI 2005 : 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Vol 4, 2005, pp. 25-30.
[251]
Z. Lu, A. Jantsch and I. Sander, "Feasibility analysis of messages for on-chip networks using wormhole routing," in PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, pp. 960-964.
[252]
Z. Lu, I. Sander and A. Jantsch, "Refinement of A Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service," in Proceedings of the Forum on Design Languages, 2005.
[253]
Z. Lu and A. Jantsch, "Traffic configuration for evaluating networks on chips," in Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, pp. 535-540.
[254]
Z. Lu and A. Jantsch, "Flit admission in on-chip wormhole-switched networks with virtual channels," in 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2004, pp. 21-24.
[255]
Z. Lu and A. Jantsch, "Flit ejection in on-chip wormhole-switched networks with virtual channels," in 22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, pp. 273-276.
[256]
Z. Lu, I. Sander and A. Jantsch, "A case study of hardware and software synthesis in ForSyDe," in Proceedings of the 15th International Symposium on System Synthesis, 2002.
Kapitel i böcker
[257]
A. Eslami Kiasari, A. Jantsch and Z. Lu, "A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs," in Algorithms in Networks-on-Chip, : Springer, 2013, pp. 21-39.
[258]
M. Liu et al., "Adaptively Reconfigurable Controller for the Flash Memory," in Flash Memories, : InTech, 2011.
[259]
A. Jantsch et al., "Memory Architecture and Management in an NoC Platform," in Scalable Multi-core Architectures : Design Methodologies and Tools, Axel Jantsch and Dimitrios Soudris Ed., 1st ed. : Springer, 2011, pp. 3-28.
[260]
A. Jantsch and Z. Lu, "Resource Allocation for QoS On-Chip Communication," in Networks-on-Chips: Theory and Practice, Fayez Gebali; Haytham Elmiligi; Mohamed Watheq El-Kharashi Ed., : CRC Press, 2009.
Icke refereegranskade
Artiklar
[261]
Z. Lu, "Guest Editorial : IEEE TC Special Issue On Communications for Many-core Processors and Accelerators," IEEE Transactions on Computers, vol. 70, no. 6, pp. 817-818, 2021.
[262]
N. Ma et al., "Design and Implementation of Multi-mode Routers for Large-scale Inter-core Networks," Integration, vol. 53, pp. 1-13, 2016.
[263]
A. Naeem et al., "Scalability of Relaxed Consistency Models in NoC based Multicore Architectures," SIGARCH Computer Architecture News, vol. 37, no. 5, pp. 8-15, 2009.
Konferensbidrag
[264]
A. Naeem, A. Jantsch and Z. Lu, "Scalability and Performance Evaluation of Memory Consistency Models in NoC based Multicore SoCs," in ICES 5th Annual Conference: World-wide Trends and Challenges in Embedded Systems (ICES 2012), 2012.
[265]
Z. Lu et al., "NNSE: Nostrum Network-on-Chip Simulation Environment," in Proceedings of Swedish System-on-Chip Conference, Stockholm, Sweden, April 2005., 2005.
[266]
Z. Lu and A. Jantsch, "Refinement for Communication-Based Design," in Swedish System-on-Chip Conference (SSoCC’03), 2003.
Avhandlingar
[267]
Z. Lu, "Design and Analysis of On-Chip Communication for Network-on-Chip Platforms," Doctoral thesis Stockholm : KTH, Trita-ICT-ECS AVH, 2007:02, 2007.
[268]
Z. Lu, "Using wormhole switching for networks on chip : feasibility analysis and microarchitecture adaptation," Licentiate thesis Stockholm : KTH, Trita-IMIT. LECS, 2005:5, 2005.
Rapporter
[269]
Z. Lu et al., "Network-on-Chip Benchmarking Specification Part 2 : Micro-Benchmark Specification," OCP-IP, 2008.
[270]
P. van der Wolf et al., "Definition of Device Level Interface with QoS : Draft Specification," IP FP6-2004-IST-4 SPRINT, 2007.
[271]
Z. Lu and A. Jantsch, "Network-on-Chip Assembler Language," Stockholm, Sweden : Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH), 2003.
Proceedings (redaktörskap)
[272]
"Highway in TDM NoC," , ACM Digital Library, 2015.
Övriga
[273]
N. Ma et al., "A 2-mW Multi-mode Router Design with Dual-core Processor in 65 nm LL CMOS for Inter-silicon Communication," (Manuscript).
[274]
F. Jafari, A. Jantsch and Z. Lu, "Weighted Round Robin Configura- tion for Worst-Case Delay Optimization in Network-on-Chip," (Manuscript).
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