Similarly to multi-core CPUs, also network devices increasingly rely on parallel packet processing engines to achieve insanely high throughput (up to 16 pipes to process 50 terabits per second on a single chip). In our recent paper accepted at ACM SIGMETRICS, we unveil, quantify, and mitigate the impact of deploying existing network monitoring mechanisms on multi-pipe network devices. Our design, called PipeCache, allows to reduce memory requirements (a constrained resource on ASIC devices) up to 16x! A PDF of the paper is available here. Code is available here.

Can one process the equivalent of 1 Tbps of traffic on a single server? In our NSDI’23 paper, we leverage disaggregation principles to push the boundary of what CPU-based packet processors can achieve in terms of throughput for a variety of network functions. For the paper PDF click here. This is a joint work with two visiting doctoral students from Roma tre University. All code is available here.

A video of Tommaso’s NSDI talk: