Publications by Yu Yang
Peer reviewed
Articles
[1]
Wang, D., Xu, J., Stathis, D., Zhang, L., Li, F., Lansner, A. ... Zou, Z. (2021). Mapping the BCPNN Learning Rule to a Memristor Model. Frontiers in Neuroscience, 15.
[2]
Yang, Y., Stathis, D., Jordao, R., Hemani, A. & Lansner, A. (2020). Optimizing BCPNN Learning Rule for Memory Access. Frontiers in Neuroscience, 14.
[3]
Stathis, D., Sudarshan, C., Yang, Y., Jung, M., Weis, C., Hemani, A. ... Wehn, N. (2020). eBrainII : a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. Journal of Signal Processing Systems, 92(11), 1323-1343.
Conference papers
[4]
Wang, D., Wang, Y., Yang, Y., Stathis, D., Hemani, A., Lansner, A., Xu, J., Zheng, L.-R., Zou, Z. (2024). FPGA-Based HPC for Associative Memory System. In 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024. (pp. 52-57). Institute of Electrical and Electronics Engineers (IEEE).
[5]
Jordao, R., Bahrami, F., Yang, Y., Becker, M., Sander, I., Rosvall, K. (2024). Multi-objective preference-free exact design space exploration of static DSP on multicore platforms. In 2024 forum on specification & design languages, FDL 2024. (pp. 59-67). Institute of Electrical and Electronics Engineers (IEEE).
[6]
Dhilleswararao, P., Ryansh, R., Boppu, S., Yang, Y., Hemani, A. (2023). Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. In Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023. (pp. 86-92). Association for Computing Machinery (ACM).
[7]
Yang, Y., Stathis, D., Hemani, A. (2022). Reducing the Configuration Overhead of the Distributed Two-level Control System. In PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022). (pp. 104-107). IEEE.
[8]
Yang, Y., Moraitis, M., Dubrova, E. (2022). Why Deep Learning Makes it Difficult to Keep Secrets in FPGAs. In DYNAMICS '20: Proceedings of the 2020 Workshop on DYnamic and Novel Advances in Machine Learning and Intelligent Cyber Security. (pp. 1-9). New YorkNYUnited States.
[9]
Xu, J., Wang, D., Li, F., Zhang, L., Stathis, D., Yang, Y., Jin, Y., Lansner, A., Hemani, A., Zou, Z., Zheng, L.-R. (2021). A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. In 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS. Institute of Electrical and Electronics Engineers (IEEE).
[10]
Stathis, D., Yang, Y., Hemani, A., Lansner, A. (2021). Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. In PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021). (pp. 685-688). Institute of Electrical and Electronics Engineers (IEEE).
[11]
Patan, A. K., Stathis, D., Dhilleswararao, P., Yang, Y., Boppu, S., Hemani, A. (2021). Design and Implementation of Optimized Register File for Streaming Applications. In 2021 25th International Symposium on VLSI Design and Test, VDAT 2021. Institute of Electrical and Electronics Engineers (IEEE).
[12]
Yang, Y., Hemani, A., Paul, K. (2021). Scheduling Persistent and Fully Cooperative Instructions. In 2021 Ieee 29Th Annual International Symposium On Field-Programmable Custom Computing Machines (Fccm 2021). (pp. 274-274). Institute of Electrical and Electronics Engineers (IEEE).
[13]
Yang, Y., Hemani, A., Paul, K. (2021). Scheduling Persistent and Fully Cooperative Instructions. In 2021 24TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2021). (pp. 229-237). Institute of Electrical and Electronics Engineers (IEEE).
[14]
Liu, L., Wang, D., Wang, Y., Lansner, A., Hemani, A., Yang, Y., Hu, X., Zou, Z., Zheng, L. (2020). A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. In 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE).
[15]
Stathis, D., Yang, Y., Tewari, S., Hemani, A., Paul, K., Grabherr, M., Ahmad, R. (2019). Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). (pp. 560-567). IEEE Computer Society.
[16]
Yang, Y., Stathis, D., Sharma, P., Paul, K., Hemani, A., Grabherr, M., Ahmad, R. (2018). RiBoSOM : Rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. In ACM International Conference Proceeding Series. (pp. 105-114). Association for Computing Machinery (ACM).
[17]
Yang, Y., Jafri, S., Hemani, A., Stathis, D. (2017). MTP-caffe : Memory, timing, and power aware tool for mapping CNNs to GPUs. In ACM International Conference Proceeding Series. (pp. 31-36). Association for Computing Machinery (ACM).
Non-peer reviewed
Theses
[18]
Yang, Y. (2022). High-Level Synthesis for SiLago : Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms (Doctoral thesis , KTH Royal Institute of Technology, Sweden, TRITA-EECS-AVL 2022:48). Retrieved from https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-317555.
Other
[19]
Yang, Y., Hemani, A. (). Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style. (Manuscript).
Latest sync with DiVA:
2025-03-21 01:01:31