Advances in Nanoelectromechanical Switch Integration

QC 20260602

Abstract

The rapid growth of data-intensive applications such as edge computing, artificial intelligence and the Internet of Things is pushing the limits of conventional CMOS electronics. In these systems, static leakage currents increasingly dominate power consumption. Nanoelectro-mechanical (NEM) switches are promising candidates for beyond-CMOS electronics due to their near-zero off-state leakage, abrupt switching characteristics, and robustness under extreme operating conditions, offering a route to dramatically reduce static power dissipation in future integrated circuits. However, practical NEM-based systems require scalable device architectures, reliable switch contacts, and CMOS-compatible integration strategies. This thesis addresses these challenges through the realization and integration of a CMOS-compatible NEM switch device library within commercial CMOS foundry platforms. The work investigates three complementary NEM switch architectures for logic and memory applications: a volatile three-terminal (3-T) switch, a volatile four-terminal (4-T) switch with decoupled actuation and signal paths, and a non-volatile seventerminal (7-T) switch. Building upon concepts established in earlier research within our group, the 3-T and 7-T devices are miniaturized and optimized through systematic studies of beam geometry and contact materials for low-voltage operation and improved switching behavior. A major contribution of this thesis is the optimization and experimental realization of the 4-T architecture, enabling body-bias-assisted reduction of the pull-in voltage and advanced circuit configurations. Two CMOS-compatible integration approaches are developed and experimentally validated: (1) Monolithic integration within the IMEC iSiPP50G silicon photonics SOI foundry platform, and (2) heterogeneous 3-D integration within the X-FAB XI10 SOI CMOS process. The first method enabled co-fabrication of all three NEM switch architectures on a single commercial foundry chip for the first time. Electrical characterization confirms volatile switching in the 3-T and 4-T devices, pull-in voltage reduction in the 4-T switch through body biasing, and both volatile and nonvolatile operation in the 7-T switch through contact engineering. However, in this approach, circuit scalability is limited by routing density inherent to planar integration, while Au contact stiction constrains switch reliability. The second approach addresses these limitations by vertically integrating the NEM device layer above the completed back-end-of-line (BEOL) through heterogeneously 3-D integration. This architecture alleviates routing constraints and improves device reliability using Ruthenium (Ru) switch contacts. Ru-coated devices demonstrate substantially improved cycling endurance, and a complementary inverter implemented with Ru-coated 3-T switches validates the feasibility of functional BEOL-integrated NEM circuits.

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