Disputationer

Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging

6 sep

Disputationer

Elektrisk mätteknik

fredag 2013-09-06, 10.00

Plats: KTH main campus, Lecture hall F3, Lindstedtsvägen 26

Respondent: Martin Lapisa , Micro and Nanosystems

2013-09-06T10:00:00.899+02:00 2013-09-06T10:00:00.899+02:00 Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging (Disputationer) KTH main campus, Lecture hall F3, Lindstedtsvägen 26 (KTH, Stockholm, Sweden)Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging (Disputationer)