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Design and Simulation of Routing and Mapping Algorithms for Interconnection Networks

An IEEE Electron Devices seminar.

Time: Thu 2018-12-06 15.00 - 16.00

Location: Lecture hall C

Participating: Masoumeh Ebrahimi

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Networks-on-Chip (NoC) has emerged as a solution to address the communication demands of many-core architectures; and it is composed of links and routers. Designing deadlock-free and fault-tolerant routing algorithms in NoCs is one of the most important issues in achieving a higher performance and better reliability. In this talk, a visualization framework for routing and mapping algorithms will be introduced. Then a systematic way to design deadlockfree routing algorithms will be presented. Finally, a reconfigurable router architecture will be suggested that allows testing multiple routers at high speed.

Biography: Masoumeh (Azin) Ebrahimi received her PhD in 2013 from University of Turku, Finland. Currently she is a researcher at KTH Royal Institute of Technology, Sweden and Adjunct professor (Docent) at university of Turku, Finland. Her current research interests include mapping and routing algorithms, reliable interconnection networks, and the application of NoC in Neural Networks.