Hello and welcome to my profile page. My name is Artur Podobas, and I am a researcher in computer systems.
Some Recent News:
- [September 2021] Check out the AI4S panel (link), where I and three other panelists will discuss the future of AI in Science! Also, happy to be reviewing for Transactions on Reconfigurable Technology and Systems (TRETS) and be part of PC of Urgent HPC (SuperComuting 2022)! Finally, our exciting workshops called CGRA4HPC and CORTEX were both accepted to IPDPS'22-- please look forward to very exciting programs!
- [July 2021] Happy to have been invited to serve on the Program Committee member on the Seventh International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'21)!
- [July 2021] Our paper on particle classification was accepted to the 2nd Workshop on Artificial Intelligence and Machine Learning for Scientific Applications. For more information, click here.
- [June 2021] Honored to have been invited to the PC of 36th IEEE International Parallel & Distributed Processing Symposium (IPDPS'22).
- [June 2021] We are organizing HPDC'21 in Stockholm (virtually!) and I (together with colleague Dong Li from UC Merced) are Poster chairs. Check it out here.
- [June 2021] Our two papers on high-performance brain-inspired neural networks (collaboration with Anders Lansner, Pawel Herman, and Naresh Ravichandran) and GPU benchmarking have been accepted to HEART. Look forward to my and student Martin Svedin presentation at HEART'21!
- [May 2021] Honored to have been invited to the PC of Workshop on Programming Environments for Heterogeneous Computing @ Supercomputing 2021.
- [May 2021] Faster Radiotherapy Plans for Cancer treatment using GPUs? Check out our recent work, where the first-year Ph.D. student Felix Liu shows the value of using GPUs for Radiation Therapy Dose Calculation. Accepted to ASHeS'21.
- [May 2021] Check out our IPDPS'21 paper on the FPGA-accelerator Spectral Elemental Method (SEM), where first-year Ph.D. candidate Martin Karp shows what it takes to for FPGAs to beat modern A100 Nvidia GPUs on Spectral Element Models (SEM) for Computational Fluid Dynamics.
- [May 2021] Is spending silicon on matrix engines worth it? Check out our paper (collaboration with Tokyo Institute of Technology and RIKEN R-CCS) on Matrix Engines in High-Performance Computing at IPDPS'21.
-  Together with colleagues from RIKEN R-CCS and TU Darmstadt, we show programmers can use OpenMP 4.0+ for automatic hardware generation AND how they can easily visualize what is going on inside the hardware using tools such as Paraver! Accepted to IWOMP'20 and Cluster'20.
-  Interested in knowing the I/O bottlenecks in your Deep-Learning pipeline? Third-year Ph.D. student Steven Wei der Chien shows how to do this in our recent work accepted to Cluster'20.
-  What are CGRAs and why should you care? Find out in my survey article published in IEEE Access.
1) IO-SEA PI (from Vetenskapsrådet side)
2) Work-package leader (WP2) for the VESTEC project on in-situ visualization
I defended my Ph.D. thesis at KTH Royal Institute of Technology in December 2015. My Ph.D. topic was on the task-based parallel programming model found in common systems such as OpenMP, Intel Cilk, Threading Building Blocks, and more. You can find my Ph.D. dissertation here. My Ph.D. supervisors were Prof. Mats Brorsson and Prof. Vladimir Vlassov. My focus was to research and explore the task-based programming model, particularly close to the hardware. For example, I built (among of the first) High-Level Synthesis tools that target automatic hardware generation directly from OpenMP tasks (if you like HLS, read my publication here and here) and also researched high-performance runtime systems to efficiently leverage such systems (best paper IWOMP'14, find it here). My Ph.D. was funded by two EC projects: ENCORE (led by Barcelona Supercomputing Centre) and PaPP (led by KTH/SICS). After my defense, I spent one year working as a post-doc at Denmark's Technical University (DTU Compute), where I was working in the COPCAMS and continued my work with high-performance OpenMP runtime systems.
In 2016, I received the prestigious JSPS scholarship and traveled to Japan to do a postdoctoral fellowship under Prof. Satoshi Matsuoka's mentorship at Matsulab at the Tokyo Institute of Technology, Japan. During this time, I was fortunate enough to work with fantastic colleagues and students, focusing on building High-Performance Hardware Accelerators using FPGAs. Amongst others, we built one of the fastest 2D and 3D Stencil Accelerators on FPGAs to this day. During this time, I also created the first high-performance Posit Arithmetic Unit for FPGAs (capable of running at hundreds of MHz).
In 2019, I was working at RIKEN Centre for Computational Science (R-CCS), which is the largest Japanese research institute and home to the top#1 supercomputer Fugaku (see TOP500 list). Here, I was working in Prof. Kentaro Sano's Processor Research Division on emerging computer architectures and non-Von-Neumann systems-- one of the leading groups in architecture in Japan.
Today, I am a researcher in Assoc. Prof. Stefano Markidis High-Performance Computing laboratory, where I lead the architectural research group.