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CREST: Coarse Grain Reconfigurable Embedded Systems Technologies

Coarse Grain Reconfigurable Architecture provides computational efficiency comparable to hardware and engineering efficiency of software. Customization will eliminate the generalities and make possible the ultra-low power embedded systems possible.

Reconfigurability allows design-reuse and ability to change and correct functionality in field. Coarse grain architecture makes reconfigurability agile and efficient, enabling dynamic reconfigurability that in turn allows many intelligent run-time features that further enhances the computational and engineering efficiency and also improves reliability that is critical in embedded systems. An integrated Model Based Development Environment as front end and a hierarchical compilation strategy that uses a library of pre-compiled domain specific functions will allow the end users to effectively use the architecture. Methodology and application templates from diverse application domains will not only validate the approach but also make adoption of the results of this project by industry easier.


This project aims to develop a a versatile, reliable and composable CGRA embedded systems platform that can deliver 1 Tera-operations/watt in 45 nm technology node, with a customisation step to eliminate generalities of CGRA to deliver the ultra-low power 10-100 Mega-operations/milliwatt.

A user friendly integrated Model Based Development (MBD) environment, using Simulink as the form end for application development, will be tightly integrated with the implementation flow: the MBD will pass not just functional input to the compiler but also energy and performance constraints and simulation/profiling statistics. The compiler in turn will output accurate estimates of energy and performance that will be back annotated into the MBD to enable efficient and accurate simulation at high-level. A structural virtual prototype will also be exported to enable simulation of structural properties.

A hierarchical compilation strategy will be developed, based on a library of pre-compiled hilgh-level building blocks to map applications to the architecture, allowing the end users to effectively use the architecture.

An adaptive, learning runtime management system to manage the resources and power in the reconfigurable embedded system platform will also be developed. This RTMS will have features to enhance the reliability of the embedded systems by implementing composable private execution environments and self-healing properties.

A set of applications from diverse domains - Automotive, Process Control and Cognitive Radio - will be developed not only to validate and demonstrate the efficacy of the architecture, methodology and RTMS, but also make adoption of the results of this project by industry easier.

An Industrial Advisory Board composed of senior scientists from ABB, Volvo, Scania, Mecel and TCS will guide the project and provide valuable feedback on direction and priorities. Active industrial
participation, together with demonstrable proof of concept results and active dissemination, will ease and encourage adoption of results by embedded systems industries in Sweden and India.


This project, which started at the end of 2010 and will run until late 2013, is a collaboration between KTH and IIT Delhi and IISc Bangalore, leveraging the existing activities and competence of the participating groups to define a challenging set of goals that are achievable within the bounds of this project and will fulfill the set objectives.

The CREST project will be divided into four work-packages, each led by a senior researcher from the four research groups involved. Each work-package will have strong contributions from all the partners ensuring a tightly knit project rather than four loosely coupled projects. Prof. Martin Törngren (KTH-MD/IEM) will lead WP1 on Model Based Development of embedded system application. Prof. Ahmed Hemani (KTH-ES/ICT) will lead the WP2 on the Crest Architecture framework. Prof. S K Nandy (IISc) will lead WP3 on Crest Compiler framework. Prof. Anshul Kumar (IIT Delhi) will lead the WP4 on RTMS.

Represented by Dr. Ranjani Narayan, Morphing Machines will be an active industrial partner that will contribute to the project implementation.

Contact Information:

Professor Ahmed Hemani (KTH ICT School) heads the project from the Swedish side, working with Martin Törngren and De-Jiu Chen from the Embedded Control Systems group at the Department of Machine Design (KTH ITM School).

Professor Anshul Kumar (CSE, IIT Delhi) leads the team from India, working with Professor SK Nandy (SERC, IISc Bangalore) and Kolin Paul (IIT Delhi).

Belongs to: Engineering Design
Last changed: May 11, 2020
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