Seminar 2016-01-27

System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems

Speaker: Li Shuo, KTH, ICT, ESY

2016-01-27

Bio

Shuo Li is a graduating PhD student in department of Electronic and Embedded Systems. His PhD defense will be at 18th Feb. 2016. By the end of 2015, he has 13 publications on system-level synthesis methodology and CGRA. He received his B.S on telecommunication engineering from Beijing Jiaotong university, Beijing, China in 2005, his M.S. on electronic engineering from K.U.Leuven, Leuven, Belgium in 2005, and his M.S. on system-on-chip design from KTH, Stockholm, Sweden in 2007.

Shuo Li is a graduating PhD student in department of Electronic and Embedded Systems. His PhD defense will be at 18th Feb. 2016. By the end of 2015, he has 13 publications on system-level synthesis methodology and CGRA. He received his B.S on telecommunication engineering from Beijing Jiaotong university, Beijing, China in 2005, his M.S. on electronic engineering from K.U.Leuven, Leuven, Belgium in 2005, and his M.S. on system-on-chip design from KTH, Stockholm, Sweden in 2007.

Abstract

System-level hardware synthesis is the evolutionary next step of high-level hardware synthesis. This seminar presents a novel system-level synthesis framework called SYLVA, which synthesizes DSP sub-systems modeled by synchronous data flow graph into hardware implementations in ASIC, FPGA or Coarse Grain Reconfigurable Architecture (CGRA) implementation styles. For ASIC and FPGA, SYLVA generates register transfer level design modules in VHDL. For CGRA, SYLVA generates CGRA configware (configuration + software) with floor plan. SYLVA synthesizes in terms of pre-characterized Function Implementations (FIMPs). It explores the design space in three dimensions: number of FIMPS, type of FIMPs, and pipeline parallelism between the producing and consuming FIMPs. The design space exploration is done by solving an automatically constructed constraint satisfaction optimization problem. SYLVA also introduces timing and interface model of FIMP to enable reuse and automatic generation of global interconnect and control to glue the FIMPs together into a working system.

SYLVA has been evaluated by applying it to several real and synthetic DSP applications and the experimental results are analyzed for the design space exploration, the global interconnect and control synthesis, the code generation, and the CGRA floorplanning features. The conclusion from the experimental results is that by exploring the multi-dimensional design space in terms of pre-characterized FIMPs, SYLVA explores a richer design space and does it more effectively compared to the existing high-level synthesis tools to improve both engineering and computational efficiency.

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